Neutral gas pressure measurements in low Earth orbit (LEO) can facilitate the monitoring of atmospheric gravity waves, which can trigger instabilities that severely disrupt radio frequency communication signals. The Space Neutral Pressure Instrument (SNeuPI) is a low-power instrument detecting neutral gas density in order to determine neutral gas pressure. SNeuPI consists of an ionization chamber and a logarithmic electrometer circuit. The Rev. 1 SNeuPI electrometer prototype does not function as designed. A Rev. 2 electrometer circuit must be designed and its performance characterized across specified operating temperature and input current ranges. This document presents a design topology for the Rev. 2 electrometer and a derivation of the theoretical circuit transfer function. Component selection and layout are discussed. A range of predicted operating input currents is calculated using modeled neutral density data for a range of local times, altitudes, and latitudes corresponding to the conditions expected for the Lower Atmosphere/Ionosphere Coupling Experiment (LAICE) CubeSat mission. Laboratory test setups for measurements performed both under vacuum and at atmospheric pressure are documented in detail. Test procedures are presented to characterize the performance of the Rev. 2 electrometer at a range of controlled operating temperatures. The results of these tests are then extrapolated in order to predict the operation of the circuit at specified temperatures outside of the range controllable under laboratory test conditions. The logarithmic conformance, accuracy, sensitivity, power consumption, and deviations from expected response of the circuit are characterized. The results validate the electrometer for use under its expected flight conditions. / Master of Science

The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step.

Variations of gas and plasma density and composition in Earth’s thermosphere and ionosphere are key indicators of interactions between different layers of Earth’s atmosphere. The nature of interactions between neutral and ion species in the upper atmosphere is an active area of study in Heliophysics and there is much to learn about the dynamic relationship between the ionosphere and neutral thermosphere. Mass Spectrometers are among an array of instruments used to explore Earth’s upper atmosphere and other space environments. In the past, data from mass spectrometers flown in low earth orbit has been used to improve atmospheric models and to study the dynamics of the ionosphere and thermosphere. Historically, these instruments are substantial in size and deployed on larger satellite platforms. Data from these larger instruments generally provide information from a specific point in time at a single location. Studies of atmospheric density and composition with multiple locations for each time point could be performed by CubeSat swarms if proper instrumentation were available to fit CubeSat payload restrictions. The proposed miniaturized time-of-flight (TOF) mass spectrometer (MS) will have a mass resolution and range sufficient for measuring the composition of Earth’s thermosphere and ionosphere while operating within the power and space constraints of a CubeSat. The capabilities of this instrument could dramatically reduce the cost of future missions while simultaneously enhancing the science return. The design employs miniaturization of TOF-MS technology, including resolution refinement techniques used for larger instruments and standard concepts for TOF-MS components such as acceleration grids, a Bradbury-Nielsen wire gate, a gridless ion mirror, and microchannel plate detector.

No description available.

No description available.

The objective of this research is to optimize silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS analog circuit building blocks for operation in extreme environments utilizing design techniques. First, negative feedback effects on single-event transient (SET) in SiGe HBT analog circuits were investigated. In order to study the role of internal and external negative feedback effects on SET in circuits, two different types of current mirrors (a basic common-emitter current mirror and a Wilson current mirror) were fabricated using a SiGe HBT BiCMOS technology and exposed to laser-induced single events. The SET measurements were performed at the U.S. Naval Research Laboratory using a two-photon absorption (TPA) pulsed laser. The measured data showed that negative feedback improved SET response in the analog circuits; the highest peak output transient current was reduced by more than 50%, and the settling time of the output current upon a TPA laser strike was shortened with negative feedback. This proven negative feedback radiation hardening technique was applied later in the high-speed 5-bit flash analog-to-digital converter (ADC) for receiver chains of radar systems to improve SET response of the system.

Être en mesure de vérifier si un circuit intégré est fonctionnel après fabrication peut s'avérer très difficile. Dans le cas des circuits analogiques et Radio Fréquence (RF) les procédures et les équipements de test nécessaires ont un impact majeur sur le prix de revient des circuits. Une approche intéressante pour réduire l'impact du coût du test consiste à mesurer des paramètres nécessitant des ressources de test faible coût et corréler ces mesures, dites mesures indirectes, avec les spécifications à tester. On parle alors de technique de test indirect (ou test alternatif) car il n'y a pas de mesure directe des spécifications, qui nécessiterait des équipements et du temps de test importants, mais ces spécifications sont estimées à partir des mesures « faibles couts ». Même si cette approche semble attractive elle n'est viable que si nous sommes en mesure d'établir une précision suffisante de l'estimation des performances et que cette estimation reste stable et indépendante des lots de circuits à traiter. L'objectif principal de cette thèse est de mettre en œuvre une stratégie générique permettant de proposer un flot de test indirect efficace et robuste. Pour être en mesure de construire cette stratégie nous avons amenés différentes contributions. Dans un premier temps, on a développée une nouvelle métrique dans cette thèse pour évaluer la robustesse des prédictions relaissées. Dans un deuxième temps, on a défini et analysé une stratégie pour la construction d'un model optimal. Cette dernière englobe un prétraitement de données ensuite une analyse comparative entre différentes méthodes de sélections de mesures indirectes aussi l'étude d'autres paramètres tels que la taille des combinaisons de mesures indirectes ainsi que celle de la taille de set d'apprentissage. Aussi on a proposé une stratégie pour une confidente exploration d'espace de mesures indirectes afin de construire plusieurs meilleurs modèles qu'on peut se servir par la suite pour résoudre des problèmes de confiance et d'optimisation. Les études comparatives réalisées ont été effectuées sur 2 cas d'études expérimentaux et à partir de métriques classiques et de la nouvelle métrique proposée permettant ainsi d'évaluer objectivement la robustesse de chaque solution.En fin, nous avons développé une stratégie complète mettant en œuvre des techniques de redondance de modèles de corrélation qui permettent d'améliorer grandement la robustesse et l'efficacité de la prise de décision en fonction des mesures obtenues. Cette stratégie est adaptable à n'importe quel contexte en termes de compromis entre le coût du test et le niveau de confiance et de précision attendu. / Being able to check whether an IC is functional or not after the manufacturing process is very difficult. Particularly for analog and Radio Frequency (RF) circuits, test equipment and procedures required have a major impact on the circuits cost. An interesting approach to reduce the impact of the test cost is to measure parameters requiring low cost test resources and correlate these measurements, called indirect measurements, with the targeted specifications. This is known as indirect test technique because there is no direct measurement for these specifications, which requires so expensive test equipment and an important testing time, but these specifications are estimated w.r.t "low-cost measurements". While this approach seems attractive, it is only viable if we are able to establish a sufficient accuracy for the performance estimation and if this estimation remains stable and independent from the circuits sets under test.The main goal of this thesis is to implement a robust and effective indirect test strategy for a given application and to improve test decisions based on data analysis.To be able to build this strategy, we have brought various contributions. Initially, we have defined new metric developed in this thesis to assess the reliability of the estimated performances. Secondly, we have analyzed and defined a strategy for the construction of an optimal model. This latter includes a data preprocessing followed by a comparative analysis of different methods of indirect measurement selection. Then, we have proposed a strategy for a confidant exploration of the indirect measurement space in order to build several best models that can be used later to solve trust and optimization issues. Comparative studies were performed on 2 experimental data sets by using both of the conventional and the developed metrics to evaluate the robustness of each solution in an objective way.Finally, we have developed a comprehensive strategy based on an efficient implementation of the redundancy techniques w.r.t to the build models. This strategy has greatly improved the robustness and the effectiveness of the decision plan based on the obtained measurements. This strategy is adaptable to any context in terms of compromise between the test cost, the confidence level and the expected precision.

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

A simple methodology for determining the input referred offset voltage of comparators is presented. This in general is difficult as the output of a comparator is discrete valued. The method relies on a Monte-Carlo-Simulation with certain comparator input values and some postprocessing of the comparator output data. The comparator is always operated in its intended environment, there is no modification of the comparator itself nor some unusual stimuli required. There is also no known restriction for the type of comparators to be analyzed.

Optical coherence tomography (OCT) and optical coherence microscopy (OCM) are non-invasive optical coherence imaging techniques, which enable micron-scale resolution, depth resolved imaging capability. Both OCT and OCM are based on Michelson interferometer theory. They are widely used in ophthalmology, gastroenterology and dermatology, because of their high resolution, safety and low cost. OCT creates cross sectional images whereas OCM obtains en face images. In this dissertation, the design and development of three increasingly complicated analog signal processing (ASP) solutions for optical coherence imaging are presented.The first ASP solution was implemented for a time domain OCT system with a Rapid Scanning Optical Delay line (RSOD)-based optical signal modulation and logarithmic amplifier (Log amp) based demodulation. This OCT system can acquire up to 1600 A-scans per second. The measured dynamic range is 106dB at 200A-scan per second. This OCT signal processing electronics includes an off-the-shelf filter box with a Log amp circuit implemented on a PCB board.The second ASP solution was developed for an OCM system with synchronized modulation and demodulation and compensation for interferometer phase drift. This OCM acquired micron-scale resolution, high dynamic range images at acquisition speeds up to 45,000 pixels/second. This OCM ASP solution is fully custom designed on a perforated circuit board.The third ASP solution was implemented on a single 2.2 mm x 2.2 mm complementary metal oxide semiconductor (CMOS) chip. This design is expandable to a multiple channel OCT system. A single on-chip CMOS photodetector and ASP channel was used for coherent demodulation in a time domain OCT system. Cross-sectional images were acquired with a dynamic range of 76dB (limited by photodetector responsivity). When incorporated with a bump-bonded InGaAs photodiode with higher responsivity, the expected dynamic range is close to 100dB.