Este trabalho estuda os efeitos de dose total ionizante (TID – Total Ionizing Dose) em amplificadores operacionais e em seus blocos básicos de construção. A radiação ionizante presente no espaço pode afetar o funcionamento das estruturas MOS, sendo que um dos parâmetros mais prejudicados é a tensão de limiar (Threshold Voltage). Em virtude da diferença nos mecanismos de aprisionamento de cargas nos óxidos dos transistores do tipo N e do tipo P, esses dois dispositivos exibem comportamentos distintos à medida que a dose acumulada aumenta referente à tensão de limiar. Por isso, foram investigados os comportamentos de dois tipos de amplificadores que podem ser ditos complementares entre si. Nesse contexto, através de simulações SPICE desvios na tensão de limiar foram promovidos através da injeção direta no arquivo de parâmetros da tecnologia considerada. Com isso, um conjunto de simulações foi feito para gerar a estimativa da tendência de comportamento de parâmetros que qualificam o desempenho dos amplificadores operacionais, como é o caso do produto ganho largura de banda (GB), ganho DC e THD (Total Harmonic Distortion). Nesse sentido, foi possível compreender os mecanismos associados à degradação de desempenho e concluir qual das duas arquiteturas pode apresentar melhor desempenho relacionado à TID. / This work studies the effects of Total Ionizing Dose (TID) in operational amplifiers as well as in their basics building blocks. The radiation from space may affect functionality of MOS structures. One the most affected parameters is the threshold voltage. Due to the difference between N-type and P-type transistors related to the mechanism of charge trapping into the oxides, these two devices exhibit different behaviors, related to the threshold voltage parameter according to accumulated dose. Therefore, this work investigates the behavior of two counterpart operational amplifiers. In this context, by means of SPICE simulations, threshold deviations are injected into the transistors by modifying the technology models of the devices. Thus, a set of simulations was performed in order to generate an estimative of tendency for some of performance parameters of operational amplifiers, such as: the gain-bandwidth product (GB), DC gain, THD (Total Harmonic Distortion). In this sense, it was possible to understand the mechanisms associated to performance degradation and also, to conclude which of both architectures is more robust related to TID.

The topic of the master´s thesis are voltage and current reference sources. There is detailed description of current and voltage references, which are basic building blocks of many analog circuits, in the theoretical part. Next part of the master´s thesis is the design of a voltage reference source, the design of a voltage reference generating two voltages and a current reference source. The correct function of all circuits have been verified using simulations, especially dependence of the output voltage or current on supply voltage or dependence of the output voltage or current when the ambient temperature is changed.

De nos jours, la conception des systèmes sur puce devient de plus en plus complexe, et requiert des densités de mémoire sans cesse grandissantes. Pour ce faire, une forte miniaturisation des nœuds technologiques s’opère. Les mémoires non-volatiles résistives, tels que les RRAM, PC-RAM ou MRAM se présentent comme des alternatives technologiques afin d'assurer à la fois une densité suffisante et des faibles contraintes en surface, en latence, et en consommation à l’échelle nanométrique. Cependant, la variabilité croissante de ces cellules mémoires ainsi que des circuits en périphérie, tels que des circuits de lecture, est un problème majeur à prendre en considération. Cette thèse consiste en une étude détaillée et une aide à la compréhension de la problématique de variabilité appliquée aux circuits de lecture pour mémoires résistives. Elle propose des solutions d’amélioration de la fiabilité de lecture de ces mémoires. Pour ce faire, diverses études ont été réalisées : revue générale des solutions existantes d’amélioration du rendement de lecture, au niveau circuit et système ; développement d’un modèle statistique évaluant la contribution à la marge de lecture de la variabilité de chaque composante du chemin de lecture de la mémoire résistive ; analyse, caractérisation, modélisation et optimisation de l’offset d’un amplificateur de lecture dynamique pour mémoires résistives ; proposition d’architecture d’amplificateur de lecture permettant un rapport signal à offset optimum. / Nowadays, Systems on chip (SoCs) conception is becoming more and more complex and demand an ever-increasing amount of memory capacity. This leads to aggressive bit cell technology scaling. Nonvolatile resistive memories (PC-RAM, RRAM, MRAM) are promising technologic alternatives to ensure both high density, low power consumption, low area and low latencies. However, scaling lead to significant memory cell and/or memory periphery variability. This thesis aims to address variability issues in read circuitries of resistive memories and propose solutions for read yield enhancement of these memories. To this end, several sub-studies were achieved: overall review of the existing solutions for read yield enhancement, at both circuit and system level; development of a statistical model evaluating the contributions to read margin of the variability of each component of the resistive memory sensing path; analysis, characterization modelling and optimization of the offset of one particular dynamic sense amplifier for resistive memories; proposal of a sense amplifier architecture that features an optimum signal to offset ratio.

Le travail réalisé lors de cette thèse s’inscrit dans le projet de création d’un calorimètre électromagnétique pour le futur International Linear Collider (ILC) au sein de la collaboration CALICE. Le calorimètre est dit ultra-granulaire du fait du grand nombre de pixels de détection : environ 82 millions dans le calorimètre final complet. C’est ce nombre élevé de détecteurs à lire qui a conduit au développement de circuits intégrés dédiés à cette tâche, l’usage d’électronique classique n’étant pas possible dans ce cas du fait de contraintes dimensionnelles. Les travaux démarrent par l’étude de la puce SKIROC2, développée par le laboratoire Omega, qui est l’état de l’art de l’ASIC de lecture pour ce projet. Les performances sur carte de test et dans l’environnement du détecteur ont été mesurées, ce qui a permis de tirer certaines conclusions sur les forces et les faiblesses de SKIROC2. Après cette étude, le travail a été le développement d’un nouvel ASIC de lecture se basant sur SKIROC2. L’objectif étant de préserver les forces de SKIROC2 tout en tentant d’en corriger les faiblesses. Le nouvel ASIC a été conçu dans une technologie tout juste disponible au moment de la conception. Il a donc tout fallu redessiner en repartant de zéro. Il s’agit en cela de building blocks plus que d’un véritable ASIC de lecture. Trois structures de préamplificateurs de charge ont été testées, l’architecture générale et le fonctionnement d’un canal de lecture étant largement inspirés de SKIROC2. / This work takes place in the design project of the electromagnetic calorimeter for the future International Linear Collider (ILC) within the CALICE collaboration. The final calorimeter will be made of 82 million of PIN diodes; this is where the term “high granularity” comes from. The need for a read-out ASIC is a consequence of this high number of detectors, knowing that the dimensions of the electromagnetic calorimeter are a big constraint: the standard electronics is not an option. This work starts from an existing ASIC called SKIROC2. This state-of-the-art read-out chip has been designed by the Omega laboratory, a member of the CALICE collaboration. The performances on testboard and in the detector environment have been measured. It allowed to conclude on the advantages and drawbacks of using SKIROC2 in the calorimeter. After that the focus has been made on the design of a new read-out chip based on SKIROC2. The main goal was to preserve the good performances of SKIROC2 while trying to correct the encountered issues. This new ASIC has been developped in a newly released technology available during the design phase. Therefore the design has been started from scratch. The final chip is composed of building blocks rather than a ready-to-use read-out chip. Three charge preamplifier designs have been tested, the general architecture of a read-out channel being largely inspired by SKIROC2.

Η ανίχνευση των δυναμικών δραστηριότητας συμβάλλει στη μείωση των δεδομένων προς αποστολή από ένα εμφυτεύσιμο σύστημα ασύρματης καταγραφής της νευρωνικής δραστηριότητας ενός ζώντα οργανισμού. Η παρούσα Mεταπτυχιακή Διπλωματική Εργασία έχει ως στόχο την σχεδίαση ενός ανιχνευτή δυναμικών δραστηριότητας σε νευρωνικές κυματομορφές ικανό να λειτουργεί σε περιβάλλον χαμηλής τάσης τροφοδοσίας για την επίτευξη μειωμένης κατανάλωσης ισχύος. Για το σκοπό αυτό, προτείνεται η σχεδίαση συστημάτων στο πεδίο του λογαρίθμου με τη χρήση MOS τρανζίστορ που είναι πολωμένα στην περιοχή υποκατωφλίου. Αρχικά, μελετώνται τα φυσικά χαρακτηριστικά των δυναμικών δραστηριότητας, δηλαδή το συχνοτικό τους περιεχόμενο και το σχήμα τους στο πεδίο του χρόνου. Επίσης, παρουσιάζεται ο μη-γραμμικός τελεστής ενέργειας και ο λόγος για τον οποίο αυτός καθίσταται σημαντικός στην επεξεργασία νευρωνικών σημάτων. Στη συνέχεια, παρουσιάζονται οι βασικές αρχές για τη σχεδίαση κυκλωμάτων στο πεδίο του λογαρίθμου. Ακόμα, κάνοντας χρήση των βασικών δομικών μονάδων του λογαριθμικού πεδίου, των μη-γραμμικών διαγωγών Ε Cells, υλοποιούνται τόσο οι συμπληρωματικοί τελεστές όσο και οι δομές επεξεργασίας σήματος που είναι απαραίτητες για την πραγματοποίηση του μη-γραμμικού τελεστή ενέργειας. Οι δομές αυτές είναι διαφοριστές και πολλαπλασιαστές τεσσάρων τεταρτημορίων τρόπου ρεύματος. Τέλος, δίνεται η ολοκλήρωση του συστήματος με την σχεδίαση ενός συγκριτή ρεύματος που επιτελεί την λειτουργία της κατωφλιοποίησης. Για την εξομοίωση του συστήματος, χρησιμοποιείται μια νευρωνική κυματομορφή, το Analog Design Environment του λογισμικού Cadence και οι παράμετροι της τεχνολογίας TSMC 130nm. / The detection of action potentials contributes to the reduction of data to be transmitted by an implantable wireless neural activity recording system. The goal of the present M.Sc. Τhesis is the design of an action potential detector capable of operating in a low-voltage environment, in order to achieve reduced power dissipation. For this purpose, the log-domain designing technique is suggested by using MOS transistors operating in the subthreshold region. Initially, the physical characteristics of action potentials are studied, i.e. the frequential content and time-domain shape. Moreover, the nonlinear energy operator is presented in addition to the reason that makes this system crucial for neural signal processing. Thereafter, the basic principles of designing log-domain circuits are presented. Furthermore, the complementary operators as well as the signal processing blocks that are necessary for the realization of NEO are implemented by using the main log-domain building units, the nonlinear transconductors E cells. The blocks required for the NEO implementation are current-mode differentiators and four-quadrant multipliers. Finally, the complete system is given after the design of a current comparator which is responsible for the operation of thresholding. The simulation of the system has been performed through the utilization of the Analog Design Environment of Cadence software and the design kit of TSMC 130nm process in addition to a neural waveform.

This work investigates the challenges associated with designing silicon-germanium (SiGe) analog and mixed-signal circuits capable of operating reliably in extreme environment conditions. Three extreme environment operational conditions, namely, operation over an extremely wide temperature range, operation at extremely low temperatures, and operation under radiation exposure, are considered. As a representative for critical analog building blocks, bandgap voltage reference (BGR) circuit is chosen. Several architectures of the BGRs are implemented in two SiGe BiCMOS technology platforms. The effects of wide-temperature operation, deep cryogenic operation, and proton and x-ray irradiation on the performance of BGRs are investigated. The impact of Ge profile shape on BGR's wide-temperature performance is also addressed. Single-event transient response of the BGR circuit is studied through microbeam experiments. In addition, proton radiation response of high-voltage transistors, implemented in a low-voltage SiGe platform, is investigated. A platform consisting of a high-speed comparator, digital-to-analog (DAC) converter, and a high-speed flash analog-to-digital (ADC) converter is designed to facilitate the evaluation of the extreme environment capabilities of SiGe data converters. Room temperature measurement results are presented and predictions on how temperature and radiation will impact their key electrical properties are provided.

Sparse approximation is a Bayesian inference program with a wide number of signal processing applications, such as Compressed Sensing recovery used in medical imaging. Previous sparse coding implementations relied on digital algorithms whose power consumption and performance scale poorly with problem size, rendering them unsuitable for portable applications, and a bottleneck in high speed applications. A novel analog architecture, implementing the Locally Competitive Algorithm (LCA), was designed and programmed onto a Field Programmable Analog Arrays (FPAAs), using floating gate transistors to set the analog parameters. A network of 6 coefficients was demonstrated to converge to similar values as a digital sparse approximation algorithm, but with better power and performance scaling. A rate encoded spiking algorithm was then developed, which was shown to converge to similar values as the LCA. A second novel architecture was designed and programmed on an FPAA implementing the spiking version of the LCA with integrate and fire neurons. A network of 18 neurons converged on similar values as a digital sparse approximation algorithm, with even better performance and power efficiency than the non-spiking network. Novel algorithms were created to increase floating gate programming speed by more than two orders of magnitude, and reduce programming error from device mismatch. A new FPAA chip was designed and tested which allowed for rapid interfacing and additional improvements in accuracy. Finally, a neuromorphic chip was designed, containing 400 integrate and fire neurons, and capable of converging on a sparse approximation solution in 10 microseconds, over 1000 times faster than the best digital solution.

Esse trabalho está baseado na investigação dos detectores de falhas aplicando classificadores de classe única. As falhas a serem detectadas são relativas ao estado de funcionamento de cada componente do circuito, especificamente de suas tolerâncias (falha paramétrica). Usando a função de transferência de cada um dos circuitos são gerados e analisados os sinais de saída com os componentes dentro e fora da tolerância. Uma função degrau é aplicada à entrada do circuito, o sinal de saída desse circuito passa por uma função diferenciadora e um filtro. O sinal de saída do filtro passa por um processo de redução de atributos e finalmente, o sinal segue simultaneamente para os classificadores multiclasse e classe única. Na análise são empregados ferramentas de reconhecimento de padrões e de classificação de classe única. Os classficadores multiclasse são capazes de classificar o sinal de saída do circuito em uma das classes de falha para o qual foram treinados. Eles apresentam um bom desempenho quando as classes de falha não possuem superposição e quando eles não são apresentados a classes de falhas para os quais não foram treinados. Comitê de classificadores de classe única podem classificar o sinal de saída em uma ou mais classes de falha e também podem classificá-lo em nenhuma classe. Eles apresentam desempenho comparável ao classificador multiclasse, mas também são capazes detectar casos de sobreposição de classes de falhas e indicar situações de falhas para os quais não foram treinados (falhas desconhecidas). Os resultados obtidos nesse trabalho mostraram que os classificadores de classe única, além de ser compatível com o desempenho do classificador multiclasse quando não há sobreposição, também detectou todas as sobreposições existentes sugerindo as possíveis falhas. / This work deals with the application of one class classifiers in fault detection. The faults to be detected are related parametric faults. The transfer function of each circuit was generated and the outputs signals with the components in and out of tolerance were analyzed. Pattern recognition and one class classifications tools are employed to perform the analysis. The multiclass classifiers are able to classify the circuit output signal in one of the trained classes. They present a good performance when the fault classes do not overlap or when they are not presented to fault classes that were not presented in the training. The one class classifier committee may classify the output signal in one or more fault classes and may also classify them in none of the trained class faults. They present comparable performance to multiclass classifiers, but also are able to detect overlapping fault classes and show fault situations that were no present in the training (unknown faults).

Esse trabalho está baseado na investigação dos detectores de falhas aplicando classificadores de classe única. As falhas a serem detectadas são relativas ao estado de funcionamento de cada componente do circuito, especificamente de suas tolerâncias (falha paramétrica). Usando a função de transferência de cada um dos circuitos são gerados e analisados os sinais de saída com os componentes dentro e fora da tolerância. Uma função degrau é aplicada à entrada do circuito, o sinal de saída desse circuito passa por uma função diferenciadora e um filtro. O sinal de saída do filtro passa por um processo de redução de atributos e finalmente, o sinal segue simultaneamente para os classificadores multiclasse e classe única. Na análise são empregados ferramentas de reconhecimento de padrões e de classificação de classe única. Os classficadores multiclasse são capazes de classificar o sinal de saída do circuito em uma das classes de falha para o qual foram treinados. Eles apresentam um bom desempenho quando as classes de falha não possuem superposição e quando eles não são apresentados a classes de falhas para os quais não foram treinados. Comitê de classificadores de classe única podem classificar o sinal de saída em uma ou mais classes de falha e também podem classificá-lo em nenhuma classe. Eles apresentam desempenho comparável ao classificador multiclasse, mas também são capazes detectar casos de sobreposição de classes de falhas e indicar situações de falhas para os quais não foram treinados (falhas desconhecidas). Os resultados obtidos nesse trabalho mostraram que os classificadores de classe única, além de ser compatível com o desempenho do classificador multiclasse quando não há sobreposição, também detectou todas as sobreposições existentes sugerindo as possíveis falhas. / This work deals with the application of one class classifiers in fault detection. The faults to be detected are related parametric faults. The transfer function of each circuit was generated and the outputs signals with the components in and out of tolerance were analyzed. Pattern recognition and one class classifications tools are employed to perform the analysis. The multiclass classifiers are able to classify the circuit output signal in one of the trained classes. They present a good performance when the fault classes do not overlap or when they are not presented to fault classes that were not presented in the training. The one class classifier committee may classify the output signal in one or more fault classes and may also classify them in none of the trained class faults. They present comparable performance to multiclass classifiers, but also are able to detect overlapping fault classes and show fault situations that were no present in the training (unknown faults).

Orientador: Jose Antonio Siqueira Dias / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-06T12:42:34Z (GMT). No. of bitstreams: 1 Oliveira_AlexVenanciode_M.pdf: 3915758 bytes, checksum: 2659008da021c19c0fea44959159f885 (MD5) Previous issue date: 2006 / Resumo: O presente trabalho tem por objetivo o projeto, desenvolvimento e montagem de um Condicionador de Sinais de baixo custo, versátil e com recursos básicos comparáveis aos equipamentos semelhantes existentes no mercado nacional, que são na sua grande maioria importados. O equipamento faz a conversão, filtragem, isolação e condicionamento de pequenos sinais de controle provenientes de diversos tipos de sensores e transdutores, comuns em ambiente industrial, utilizando uma tecnologia bem consolidada de transporte de sinais em malhas de controle industriais: o transporte no modo corrente de 4-20mA. Esta tecnologia, mesmo frente à novos desenvolvimentos digitais na área de controle e transmissão de sinais em ambiente industrial, resiste como alternativa econômica e de ótimos resultados, mesmo em ambientes extremamente agressivos, com altos níveis de interferência / Abstract: In this work it is presented the design, development and implementation of a low cost and versatile signal conditioner which is similar to the products available in the Brazilian market, most of them imported. The developed equipment performs the conversion, filtering, isolation and conditioning of small control signals from various types of sensors and transducers commonly used in industrial environments, by using a mature technology of signal transport in industrial control loops: current mode of 4-20mA. This technology, despite of new digital developments in the area of control and signal transmission in industrial environments, resists as an economic alternative with excellent results, especially in extremely aggressive environments with high levels of interference / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica