In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long time operation. As a fundamental building block of ADC, comparator should support a tightened power budget. Therefore, developing low-power design techniques for comparator is becoming more and more important. As an alternative to the conventional voltage-mode comparator, this thesis proposed an energy efficient time-domain comparator, which uses digital circuits to process analog signals by representing them as timing information. The proposed time-domain comparator has three main features: comparing on both clock edges (rising/falling), asynchronous comparison and 2-bit/step comparison. With these features, power consumption of the comparator can be effectively reduced. For verification, the proposed time-domain comparator is fabricated in IBM 0.18um CMOS technology in comparison with other two conventional time-domain comparators working at 100kS/s sampling rate and 8-bit resolution. The achieved power consumption of the proposed time-domain comparator is 50nW, which is much lower than 84nW and 285nW of the other two time-domain comparators.

Oversampling analog-to-digital and digital-to-analog converters are gaining more popularity in many signal processing applications. Delta-sigma modulators are used in practical applications of oversampling systems because of their apparent practical advantage over other oversampling converters in terms of insensitivity to the inevitable imperfection of the analog circuitry. In Δ∑ modulators, analog integrators are always very important components and are usually modeled as ideal in real applications. However, theoretical analysis shows that the integrator nonideality due to capacitor mismatching and finite op-amp gain cause large signal-to-noise ratio degradation. The primary disadvantages of the dual-quantization and cascade modulators are that they rely on the precise cancellation of terms derived from two separate circuits, one analog and one digital, and that there are added complexities on the digital sides. This thesis describes digital adaptive correction of nonidealities in dual-quantization and cascade modulators. The sources and effects of nonidealities in a first-order delta-sigma loop are analyzed. Simple correction schemes are presented, and theoretical SNR improvements are calculated and compared with simulation results. / Graduation date: 1993

Thesis (M.S.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaf 41). Also available on the World Wide Web.

Thesis (M.S.)--Ohio University, November, 1985. / Title from PDF t.p.

Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references. Also available on the World Wide Web.

Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2008/05/12). Includes bibliographical references.

Thesis (Ph. D.)--University of Hong Kong, 2008. / Includes bibliographical references. Also available in print.

Thesis (Ph. D.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 65-68). Also available on the World Wide Web.

Thesis (M.S.)--Ohio University, November, 1997. / Title from PDF t.p.

Thesis (Ph.D.)--Mathematics, Georgia Institute of Technology, 2008. / Committee Chair: Yang Wang; Committee Member: Christopher Heil; Committee Member: Doron Lubinsky; Committee Member: Guillermo Goldsztein; Committee Member: Steven W. McLaughlin