Pipelined analog to digital converters (ADCs) are very important building blocks in many electronic systems such as high quality video systems, high performance digital communication systems and high speed data acquisition systems. The rapid development of these applications is driving the design of pipeline ADCs towards higher speed, higher dynamic range, lower power consumption and lower power supply voltage with the CMOS technology scaling. This trend poses great challenges to conventional pipelined ADC designs which rely on high-gain operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the accuracy limit set by analog building blocks (opamps and capacitors) in the context of low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted correlated double sampling (CDS) technique which addresses the finite opamp gain effect and the other is the radix-based background digital calibration technique which can take care of both finite opamp gain and capacitor mismatch. These methods are simple, easy to implement and power efficient. The effectiveness of the proposed techniques is demonstrated in simulation as well as in experiment. Two prototype ADCs have been designed and fabricated in 0.18μm CMOS technology as the experimental verification of the proposed techniques. The first ADC is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in amplifier design is achieved with this gain boosting. Measurement results show total power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel correlation-based background calibration to enhance the linearity. The linearity limit set by the capacitor mismatches, finite opamp gain effects is exceeded. After calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power consumption is 12mW from 0.9V supply when operating at 2MSPS. / Graduation date: 2004

This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of the DAC error is indicated through a simple model for unit-element based DACs. The impact of the DAC error on the performance of ADC is then analyzed. Various techniques dealing with the DAC error are described and their drawbacks are pointed out. Based on the nature of the DAC error and the surrounding signals, a fully digital method to estimate the error from the ADC output and remove it is proposed. Simulation results are shown to support the effectiveness of the method. Simulations also show that the proposed technique can work together with the technique of adaptive compensation for quantization noise leakage in cascaded delta sigma (MASH) ADC cases. These two techniques are the foundation for the design of high speed, high resolution delta sigma ADCs with relaxed requirements on the analog circuits. To verify the proposed technique, an experimental MASH ADC was built, including the design and fabrication of a chip of a second-order multi-bit delta sigma ADC in a 1.6��m CMOS technology. The measured results show that the proposed DAC correction technique is highly effective. / Graduation date: 2004

A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-��m quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD) is -81dB and -65dB with an input signal frequency of 100KHz and 10MHz, respectively. This is the best performance reported to date for a CMOS implementation. / Graduation date: 2003

This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique for the compensation of opamp input-referred offset and clock-feedthrough effect is examined and improved to achieve continuous operation. Experimental results show that after the compensation, the SC integrator's output signal swing is greatly increased. The effects of the analog circuitry nonidealities in delta-sigma ADCs are also analyzed. The analysis shows that the nonidealities in cascaded delta-sigma ADCs cause noise leakage, which limits the overall performance of the cascaded modulators. In order to reduce the noise leakage, a novel adaptive compensation technique is proposed. To verify the effectiveness of the proposed compensation techniques, a prototype 2-0 cascaded modulator was designed. Its first stage, a second-order delta-sigma modulator with test signal input circuit, was designed and fabricated in 1.2 ��m CMOS technology. The measurement results show that the noise leakage is reduced effectively by the compensation, and the performance of the cascaded delta-sigma modulator is greatly improved. / Graduation date: 1999

The advance of digital IC technology has been very fast, as shown by rapid development of DSP, digital communication and digital VLSI. Within electronic signal processing, analog-to-digital conversion is a key function, which converts the analog signal into digital form for further processing. Recently, low-voltage and low-power have become also an important factors in IC development. This thesis investigates some novel techniques for the design of low-power high-performance A/D converters in CMOS technology, and the non-ideal switched-capacitor effects of (SC) circuits. A new successive-approximation A/D converter is proposed with a novel error cancellation scheme. This A/D converter needs only a simple opamp, a comparator, and a few switches and capacitors. It can achieve high resolution with relative low power consumption. A new ratio-independent cyclic A/D converter is also proposed with techniques to compensate for the non-ideal effects. The implementation include a new differential sampling that is used to achieve ratio-independent multiple-by-two operation. Extensive simulations were performed to demonstrate the excellent performance of these data converters. / Graduation date: 1999

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters (ADCs and DACs). Most delta-sigma modulators in production today employ single-bit quantization because a 1-bit DAC is inherently linear, whereas a multi-bit DAC is not. Were it not for this drawback, the use of multi-bit quantization would improve a delta-sigma modulator's performance by increasing the modulator's resolution or increasing the modulators's bandwidth, while at the same time whitening the quantization noise and improving modulator stability. This thesis explores the element-mismatch-shaping technique, which attenuates the noise caused by static element mismatch in a multi-level DAC by a method similar to delta-sigma modulation. Existing element-matching techniques are reviewed and some analytical and architectural work related to the realization of mismatch-shaping logic is presented. A custom switched-capacitor (SC) DAC is used to verify various element mismatch-shaping algorithms. Experiments show that mismatch-shaping can reduce harmonic distortion by up to 30 dB. / Graduation date: 1998

Multi-level decision feedback equalization (MDFE) is a sampled signal processing technique for data recovery from magnetic recording channels which use the 2/3(1,7) run length limited code. The key adaptive feedback loops in MDFE are those which perform the timing recovery, gain recovery, dc offset detection, and adaptive equalization of the feedback equalizer. The algorithms used by these adaptive loops are derived from the channel error which is the deviation of the equalized signal from its ideal value. It is advantageous to convert this error signal to a digital value using a flash analog-to-digital converter (flash ADC) to simplify the implementation of the adaptive loops. In this thesis, a scheme to place the thresholds of the flash ADC is presented. The threshold placement has been optimized based on the steady-state probability density function (pdf) of the signal to be quantized. The resolution constraints imposed by this quantization scheme on the adaptive loops has been characterized. As the steady-state assumption for the signal to be quantized is not valid during the transient state of the adaptive loops, the loop transients with this quantization scheme have been analyzed through simulations. The conditions under which the channel can recover from a set of start-up errors and converge successfully into steady-state have been specified. The steady-state channel performance with the noise introduced by the iterative nature of the adaptive loops along with this quantization scheme has also been verified. / Graduation date: 1997

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 106-110). Also available on the World Wide Web.

A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivator for using the SOI CMOS technology instead of bulk CMOS seems to be the smaller gate leakage power consumption. The targeted applications in mind for the ADCs are read channel and ultra wideband radio applications. These applications requires a resolution of at least four to six bits and a sampling frequency of above 1 GHz. Hence the flash ADC topology is chosen for the implementations. In this work we do also propose enhancements to the flash ADC converter. Further, this work also investigates introduction of dynamic element matching (DEM) into a flash ADC. A method to introduce DEM into the reference net of a flash ADC is proposed and evaluated. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a top-down design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level using MATLAB and SpectreHDL. The modeling results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC implementation has a conventional topology. It has a resistor net connected to a number of latched comparators and employs a ones-counter thermometer-to-binary decoder. This ADC serves as a reference for evaluating the other topologies. The measurements indicate a maximum sampling frequency of 470 MHz, an SNDR of 26.3 dB, and an SFDR of about 29 to 35 dB. The second ADC has a similar topology as the reference ADC, but its thermometer-to-binary decoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact decoder with a regular structure and a short critical path. The measurements show that it is more efficient in terms of power consumption than the ones-counter decoder and it has 40 % smaller chip area. Further, the SNDR and SFDR are similar as for the reference ADC, but its maximum sampling frequency is about 660 MHz. The third ADC demonstrates the introduction of DEM into the reference net of a flash ADC. Our proposed technique requires fewer switches in the reference net than other proposals. Our technique should thereby be able to operate at higher sampling and input frequencies than compared with the other proposals. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB in average when introducing DEM. The transistor level simulations in Cadence and measurements of the ADC with DEM indicates that the SFDR improves by 6 dB and 1.5 dB, respectively, when applying DEM. The smaller improvement indicated by the measurements is believed to be due to a design flaw discovered during the measurements. A mask layer for the resistors of the reference net is missing, which affects their accuracy and degrades the ADC performance. The same reference net is used in the other ADCs, and therefore degrades their performance as well. Hence the measured performance is significantly lower than indicated by the transistor level simulations. Further, it is observed that the improved SFDR is traded for an increased chip area and a reduction of the maximum sampling frequency. The DEM circuitry impose a 30 % larger chip area.

The main purpose of this thesis is to research High-Order Sigma-Delta Analog-to-Digital converter for precision measurement, a PI compensator and a third-order Sigma-Delta modulator has been proposed based on a second-order Sigma-Delta modulator. In accordance with the analysis result of frequency domain and time domain of system, we use third-order model because of better response with auxiliary software to simulate and implement the system, then measure modulator output variance for input variation. This converter circuit demonstrates that it can achieve the requirements of precision and linearity which the measure instrument demands.