Flash Analog-to-Digital Converters (ADCs), targeting optical communication standards, have been reported in SiGe BiCMOS technology. CMOS implementation of such designs faces two challenges. The first is to achieve a high sampling speed, given the lower gain-bandwidth (lower ft) of CMOS technology. The second challenge is to handle the wide bandwidth of the input signal with a certain accuracy. Although the first problem can be relaxed by using the time-interleaved architecture, the second problem remains as a main obstacle to CMOS implementation. As a result, the feasibility of the CMOS implementation of ADCs for such applications, or other wide band applications, depends primarily on achieving a very small input capacitance (large bandwidth) at the desired accuracy. In the flash architecture, the input capacitance is traded off for the achievable accuracy. This tradeoff becomes tighter with technology scaling. An effective way to ease this tradeoff is to use resistive offset averaging. This permits the use of smaller area transistors, leading to a reduction in the ADC input capacitance. In addition, interpolation can be used to decrease the input capacitance of flash ADCs. In an interpolating architecture, the number of ADC input preamplifiers is reduced significantly, and a resistor network interpolates the missing zero-crossings needed for an N-bit conversion. The resistive network also averages out the preamplifiers offsets. Consequently, an interpolating network works also as an averaging network. The resistor network used for averaging or interpolation causes a systematic non-linearity at the ADC transfer characteristics edges. The common solution to this problem is to extend the preamplifiers array beyond the input signal voltage range by using dummy preamplifiers. However, this demands a corresponding extension of the flash ADC reference-voltage resistor ladder. Since the voltage headroom of the reference ladder is considered to be a main bottleneck in the implementation of flash ADCs in deep-submicron technologies with reduced supply voltage, extending the reference voltage beyond the input voltage range is highly undesirable. The principal objective of this thesis is to develop a new circuit technique to enhance the bandwidth-accuracy product of flash ADCs. Thus, first, a rigorous analysis of flash ADC architectures accuracy-bandwidth tradeoff is presented. It is demonstrated that the interpolating architecture achieves a superior accuracy compared to that of a full flash architecture for the same input capacitance, and hence would lead to a higher bandwidth-accuracy product, especially in deep-submicron technologies that use low power supplies. Also, the gain obtained, when interpolation is employed, is quantified. In addition, the limitations of a previous claim, which suggests that an interpolating architecture is equivalent to an averaging full flash architecture that trades off accuracy for the input capacitance, is presented. Secondly, a termination technique for the averaging/interpolation network of flash ADC preamplifiers is devised. The proposed technique maintains the linearity of the ADC at the transfer characteristics edges and cancels out the over-range voltage, consumed by the dummy preamplifiers. This makes flash ADCs more amenable for integration in deep-submicron CMOS technologies. In addition, the elimination of this over-range voltage allows a larger least-significant bit. As a result, a higher input referred offset is tolerated, and a significant reductions in the ADC input capacitance and power dissipation are achieved at the same accuracy. Unlike a previous solution, the proposed technique does not introduce negative transconductance at flash ADC preamplifiers array edges. As a result, the offset averaging technique can be used efficiently. To prove the resulting saving in the ADC input capacitance and power dissipation that is attained by the proposed termination technique, a 6-bit 1.6-GS/s flash ADC test chip is designed and implemented in 0.13-$\mu$m CMOS technology. The ADC consumes 180 mW from a 1.5-V supply and achieves a Signal-to-Noise-plus-Distortion Ratio (SNDR) of 34.5 dB and 30 dB at 50-MHz and 1450-MHz input signal frequency, respectively. The measured peak Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL) are 0.42 LSB and 0.49 LSB, respectively.

I denna uppsats undersöks huruvida en lyssnare kan skilja på två ljudmixar som är mixade på samma sätt men summerade på olika sätt. Den ena summeras analogt och den andra digitalt. Om så är fallet, hur tycker lyssnaren att dessa skillnader yttrar sig? Som metod fick en testpanel i ett blindtest lyssna på två olika mixar, en rocklåt och en jazzlåt, som båda fanns i både analogt och digitalt summerade versioner. Dessa fick testsubjekten sedan besvara några frågor kring och tycka till om dessa olika versioner i en kvalitativ enkätundersökning Det visade sig att skillnader uppfattades av merparten av lyssnarna. Den vanligast förekommande beskrivningen var att det var skillnad på stereobredd, djup och dynamik i mixarna beroende på hur de summerats. Även ord som klarhet, värme och tydlighet förekom. Testpanelen var överlag även väldigt bra på att gissa vilken version som var summerad på vilket sätt. Dessa gissningar verkar i på många fall vara baserad på den förutfattade meningen att analogt borde vara bättre. Det är ganska tydligt att detta forskningsarbete i mångt och mycket är en fallstudie för just de variabler som förekom (märke på den analoga summeraren, ljudkvalité på de inspelade ljudet, programmaterial med mera). Fler tester och undersökningar behövs för att kunna dra generella slutsatser.

This work lays out the development of a reconfigurable electronic system, which is composed of biologically relevant circuits. This system has been termed a Field-Programmable Neuron Array (FPNA) and is analogous to the more familiar Field-Programmable Gate Array (FPGA) and Field-Programmable Analog Array (FPAA). At the core of the system is an array of output somas based on previously developed bio-physically based channel models. Linking them together is a complex 2D dendrite matrix, FPAA-like floating-gate routing, and associated support circuitry. Several levels of generality give this system unprecedented re-configurability. The dendrite matrix can be arbitrarily configured so that many different topologies of dendrites can be investigated. Different soma circuits can be connected / disconnected to / from the dendrite matrix. Outputs from the somas can be arbitrarily routed to input synapses that exist at each dendrite node as well as the soma nodes. Lastly, the dynamics of each node consist of a mixture of individually tunable parts and global biases. All of this can be configured in concert to investigate neural circuits that exist in biological systems. This chip will have a significant impact on research in many fields including neuroscience, neuromorphic engineering, and robotics. This chip will allow for rapid prototyping of spinal circuits. Since the fundamental circuits of the system are chosen to be biologically relevant, outputs from the various nodes should also be relevant, thus yielding itself to use by neuroscientists. This system also provides a tool by where biological systems can be emulated in real-world electronic systems. Solutions to many problems faced by roboticists (such as bi-pedal standing / walking / running / jumping / climbing and the transitions between states) are present in biology. By providing a chip that can duplicate the same neural circuits that are responsible for these processes in the biology, the hypothesis is that researchers can begin to solve some of the same types of problems in artificial systems.

When designing analog circuits, we must ultimately perform measurements on the fabricated chips to determine whether they work correctly or not. The test results are compared with simulation results to determine what the differences to the expected results are. Therefore, incremental improvement and redesign becomes possible. We can obtain highly important information from the test results, making circuit testing a very important aspect of the process of analog circuit design. Especially, measurements during the development phase may include internal circuit nodes which will not be accessible in a final design but are pinned out specifically in the development phase. Because the probing tools present capacitive loads to the circuit, these additional loads may affect the analog circuits‟ response, especially in a high frequency range. Therefore, decreasing influence of capacitive loads of the probing tools in the testing environment is very important. We use analog buffers to separate the analog circuit node from the probing tools. Therefore, the buffer becomes a very important block in analog circuit testing [1-3]. For adapting to different testing environments, this thesis examines three different types of buffer which are designed using a partially modular method [4, 5]. All buffers provide a DC to 1 MHz bandwidth. The first buffer module provides a -1.3 V~1.3 V signal range driving 25 pf~85 pf capacitive loads; the second buffer has a -0.8 V~0.8 V range with for 5 pf~25 pf loads; the third buffer yields -0.5 V~0.5 V range with 1 pf~5 pf loads. The circuit design is discussed and simulated results are presented. Finally, measured results are reported for an open-loop output stage with near unity gain (buffer three). This circuit was previously fabricated in 0.35 £gm CMOS technology.

Thesis (M.S.)--Missouri University of Science and Technology, 2009. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 25, 2009) Includes bibliographical references (p. 23-24).

Thesis (M.A.)--Kutztown University of Pennsylvania, 2000. / Source: Masters Abstracts International, Volume: 45-06, page: 2707. Typescript. Abstract precedes thesis title page as [2] preliminary leaves. Copy 2 in Main Collection. Includes bibliographical references (leaves 108-115).

Thesis (Ph.D.)--Drexel University, 2008. / Vita. Includes bibliographical references (leaves 204-209). Online version available

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Includes bibliographical references (p. 118-120).

Thesis--M. Sc.(Eng.)--University of Hong Kong. / Mimeographed.