Bakgrund: Obehandlad postoperativ smärta kan leda till ett flertal komplikationer och försenat tillfrisknande. För adekvat smärtbehandling bör smärtan utvärderas regelbundet med en smärtskattningsskala som patienterna informerats om i det preoperativa skedet.Syfte: Studiens syfte var att undersöka hur patienter upplever smärtskattning postoperativt samt att undersöka om patienterna ansåg att de fått tillräckligt med information preoperativt om visuell analog skala (VAS) för att kunna tillämpa den postoperativt. Syftet var även att undersöka om ålder och genus har någon inverkan på smärtskattning.Metod: Enkäter delades ut på fyra vårdavdelningar på Akademiska sjukhuset, Uppsala. Det var 38 patienter i åldrarna 18-80 år som deltog i studien.Resultat: Tre patienter av 38 fick såväl muntlig som skriftlig information om smärtskattning preoperativt. Yngre patienter upplevde att informationen var tillräcklig i större utsträckning än de äldre patienterna (p=0,04). De patienter som vid tidigare vårdtillfälle använt VAS hade lättare att tillämpa smärtskattningsskalan vid det aktuella vårdtillfället (p=0,003). Det var 94,4% (34/36) av patienterna som ansåg att de fick skatta sin smärta tillräckligt ofta den första postoperativa dagen.Slutsats: Den postoperativa smärtskattningen upplevdes tillfredställande av patienterna. De ansåg dock att det fanns brister i den preoperativa informationen om smärtskattning.

High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F&I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F&I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F&I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35μm CMOS process to verify the ideas. The S/H and F&I ADC prototype is realized in 0.35μm double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate.

The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area. Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported. In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results.

This thesis presents a stable technique for distribution of data in Time Interleaved Digital-to-Analog Converters (TIDAC) that allows usage of the entire Nyquist bandwidth. The data distribution uses a Thiran all-pass filter to ensure stability and preserve the phase in the bandwidth of interest. Also, an online technique to compensate for the gain error mismatch in different channels and a skew error calibration technique for open loop configuration is proposed. For the over-all sampling rate of FS, i.e. bandwidth of FS/2 (according to Nyquist), this proposed technique allows calibration of skew error for input signal for most of the Nyquist bandwidth where frequency translation is applied to the input signal to provide calibration in the lower half of the Nyquist band. The simulation results for a 2-channel 14-bit current steering binary weighted TIDAC shows a substantial improvement in SNDR after calibration for input signals up to Nyquist frequency.

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