As CMOS processes size continues to shrink, a number of factors limit the ability of analog circuit performance to scale with the process. These issues include smaller transistor intrinsic gains and lower supply voltages. However, scaling continues to increase the speed and decrease the power of digital circuits. In this thesis, an active time-based integrator is proposed to replace amplifiers. The integrator, implemented using highly digital ring oscillators, seeks to take advantage of benefits offered by technology scaling while negating the issues of low gain and low supply voltages. The proposed integrator topology is used in a 20MHz 4th order continuous-time analog filter. Designed in a 90nm CMOS process, the time-based continuous-time filter achieves superior noise and linearity performance compared to state-of-the-art conventional active RC filters in simulations. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from June 17, 2011 - June 17, 2012

In this dissertation, a new ����� A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure, which can realize a high maximum out-of-band quantization noise gain while maintaining stable operation and thus achieve 14-bit resolution at 8 times oversampling. A fifth-order ����� analog-to-digital converter (A/D) has been designed and tested in a 0.18 ��m CMOS process. This is the first single-stage ����� A/D converter reported in the literature that achieves 14-bit resolution at 4 MHz equivalent Nyquist rate with a 1.8-V power supply. / Graduation date: 2002

The precise measurement of a capacitance difference or ratio in a digital form is very important for capacitive sensors, for CMOS process characterization as well as for the realization of precise switched-capacitor data converters, amplifiers and other circuits utilizing ratioed capacitors. This thesis introduces design techniques for on-chip capacitor ratio testing and sensor readout that utilize sigma-delta modulation and integrate the sensor capacitors into the modulator. Several single-ended circuits are introduced, and the correlated-double-sampling (CDS) technique is used in the circuits to reduce the non-ideal effects of opamps. Several simple calibration schemes for clock-feedthrough cancellation are also introduced and discussed. A fully-differential implementation is also described and various common-mode feedback schemes are discussed and analyzed. Simulation and experimental results show that these circuits can provide extremely accurate results even in the presence of non-ideal circuit effects such as finite opamp gain, opamp input offset and noise, and clock-feedthrough effect from the switches. To verify the effectiveness of the circuits and simulations, two prototype chips containing a single-ended realization and a fully-differential one were designed and fabricated in a 1.2 ��m CMOS technology. Two off-chip mica capacitors were used in the test circuits, and the measured results show that very accurate results can be obtained using these circuit techniques even with off-chip noise coupling and large parasitic capacitances. / Graduation date: 1999

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. A recent development in the realm of delta-sigma-based ADC and DAC systems is the use of multilevel (as opposed to binary) quantization. This development owes its existence to the discovery of a variety of techniques which cause linearity errors of the embedded multilevel DAC to be attenuated in the frequency band of interest. This thesis presents several methods for shaping the DAC element mismatch error and reducing the dynamic error in the band of interest. To demonstrate the effectiveness of the proposed algorithms, a current-mode unit element DAC is designed and used as a test bed. Both theoretical analysis and experimental results show that these methods can greatly attenuate the noise in the band of interest. The methods presented in this thesis will allow high performance, high-frequency wideband delta-sigma modulators to be constructed. / Graduation date: 1998

Delta-sigma data converters have gained popularity in both analog-to-digital and digital-to-analog converters (ADCs and DACs) due to their simplicity, high linearity and immunity to many analog circuit imperfections. These data converters include features such as oversampling, noise-shaping, and (historically) single-bit quantization. Single-bit converters are preferred for their inherent linearity. This is a feature which multibit converters cannot realize due to the unavoidable phenomenon of element mismatch. Because of this problem, multibit converters have been largely unexplored, and the market has seen few multibit commercial products. Earlier work has shown that multibit DACs constructed with unit elements can be applied in an architecture which shapes the spectrum of the noise caused by element mismatch. The basis of this thesis is the experimental verification of such a DAC. A Xilinx 4005 FPGA is utilized to implement a 3rd-order 4-bit delta-sigma modulator and the mismatch-shaping logic, while a custom IC consisting of 16 individually-controlled differential current sources implements the unit-element DAC. The final DAC achives a Spurious Free Dynamic Range (SFDR) of 96 dB at a sampling rate of 62.5 kHz. / Graduation date: 1997

Decision Feedback Equalization (DFE) in a data recovery channel filters the bit decision in the current symbol period in generating the sample at the comparator in the subsequent clock period. The operations of sampling, comparing, filtering the decision bits into a feedback signal, and subtraction of that feedback signal are cascaded, thereby establishing the critical timing path. Thus, this system, though simple, requires its components to have large bandwidths in order to achieve the high-speed response necessary to perform the described feedback function. For the entire system to run at speeds comparable to those of competing technologies (100MHz to 250MHz), the components must have bandwidths greater than 100MHz, and work together to provide a loop bandwidth of at least 100MHz. A 300MHz latching comparator and a 125MHz 6-bit current-DAC were designed in a 5V, 1 um CMOS n-well process for use in a DFE loop. Both blocks are fully differential and achieve an accuracy of 1/2 LSB (10uA) over a differential signal range of 1.28mA. This is true for their operations at speed, in isolated simulation and as contiguous blocks. The DAC power consumption is relatively high at 23mW, due to internal switching circuits which require a static current, but the comparator's power consumption is minimal at 5mW. / Graduation date: 1997

Oversampled delta-sigma modulation is one of the widely used A/D conversion techniques for narrow bandwidth signals. In this study several new lowpass and bandpass delta-sigma modulator architectures as well as novel pseudo-N-path integrators that can be used in implementing these architectures are proposed. By using multiplexing techniques the new lowpass delta-sigma modulator architectures exchange higher clock rates with hardware complexity. For a given oversampling ratio (OSR), the multiplexed first-order delta-sigma modulator achieves a higher resolution. Guaranteed stability is a very desirable feature of these structures. The multi-loop delta-sigma modulator architecture similarly reduces the number of integrators needed to achieve high-resolution conversion for a given OSR. To ensure stability a quantizer with (N+1) bits must be used, where N is the number of loops, or in other words, the order of the delta-sigma modulator. Digital correction or randomizing techniques can be used to eliminate the performance reduction due to digital-to-analog- (D/A) converter nonlinearity error [59], [64]. Bandpass delta-sigma modulators are useful for applications such as AM radio receivers, spectrum analyzers, and digital wireless systems. Using z --> -z[superscript N] or z --> z[superscript N] mapping, a low pass delta-sigma modulator can be transformed to a bandpass one. One of the methods to implement the loop filters in bandpass delta-sigma modulators is to use Pseudo-N-Path (PNP) switched-capacitor (SC) integrators. The advantage is that the center frequency occurs exactly at an integer division of the sampling frequency because of the number of physical paths. To achieve maximum resolution, integrators that do not suffer from clock feedthrough peaks are needed. The proposed differential and single-ended novel PNP integrators address this problem [76]. To keep the opamp specifications less stringent while achieving high resolution, these PNP integrators have been further improved with gain compensation techniques [53]. / Graduation date: 1997

Graduation date: 1995

Graduation date: 1994

Graduation date: 1994