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While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. Two FPAAs, built using Multiple Input Translinear Elements (MITEs), have been designed, fabricated, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, current splitters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. Supporting circuitry for interfacing with current-mode, translinear FPAAs has also been developed. This circuitry included a voltage-to-current converter, a current-to-voltage converter, and a pipelined analog-to-digital converter. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.

Abstract The static linearity testing of analog-to-digital and digital-to-analog converters (ADCs and DACs) has traditionally required test instruments with higher linearity and resolution than that of the device under test. In this thesis ways to test converters without expensive precision instruments are studied. A novel calculation algorithm for the ADC differential non-linearity (DNL) and integral non-linearity (INL) estimation is proposed. The algorithm assumes that two stimuli with constant offset between them are applied to the ADC under test and that the code density histograms for both stimuli are recorded. The probability density function (PDF) of the stimulus is then solved using simple calculations so that DNL and INL of the ADC can be estimated without a priori known stimuli. If a DAC is used to generate the stimulus to ADC, all inputs and outputs are digital and the new algorithm can be used to obtain the PDF of the DAC output. Moreover, the PDF of DAC actually characterizes its INL and DNL so that this all-digital test configuration enables a simultaneous testing of both converters thanks to the new algorithm. The proposed algorithm is analyzed thoroughly both mathematically and by carrying out several simulations and experimental tests. On the basis of the analysis it is possible to approximate the impending estimation error and select the optimal value for the offset between the stimuli. In theory, the accuracy of the algorithm proposed equals that of the standard histogram method with ideal stimulus, but in practice, the accuracy is limited by that of the offset between the stimuli. Therefore, special attention is paid to development of an accurate and small offset generator which enables ratiometric test setup and solves the problems in the case of reference voltage drift. The proposed on-chip offset generator is built using only four resistors and switches. It occupies 122·22 μm2 in a 130 nm CMOS process and accuracy is appropriate for the INL testing of 12-bit converters from rail-to-rail. Based on the analysis of the influence of resistor non-linearity on the accuracy of offset, it is possible to improve the offset generator further. With discrete resistors, the INL of 16-bit ADCs was tested using a 12-bit signal generator. The proposed simple algorithm and tiny offset generator are considered to be important steps towards built-in DNL and INL testing of ADCs and DACs.

No description available.

LD2668 .T4 1966 A988 / Master of Science

Call number: LD2668 .T4 1984 S63 / Master of Science

International Telemetering Conference Proceedings / October 29-November 02, 1990 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The concepts of modulation index and FM improvement are simple and straightforward when the modulating signals are sinesoidal. For a complex baseband waveform such as analog TV, the FM improvement may be seriously underestimated. A method for computer simulation of video waveforms and the resulting spectra are presented.

Nowadays, Sigma-Delta analog-to-digital converters have been widely used in the technology of analog-to-digital conversion. It depends on the merits that the approach of Sigma-Delta has. The signal converted by oversampling is precise and well-suited in signal processing systems.This thesis mainly focuses on the principles and simulations of fundamental first-order Sigma-Delta converter, and some brief introductions about other Sigma-Delta converters.The main researches of this thesis are as follows: (1)This thesis shows not only the path about development of technology of different ADCs, but also the features and principles of these ADCs and their structures. (2)The thesis discusses how the technologies of oversampling and noise shaping are used in Sigma-Delta analog-to-digital conversion. (3)Illustrate different orders Sigma-Delta converters in different bits and their advantages and disadvantages, respectively. (4)The simulation is given in Matlab(Simulink). Typical first-order SigmaDelta converter is simulated with additional noise which will impact the input signal when implement. / Sigma-Delta Converter

published_or_final_version / Electrical Engineering / Master / Master of Science in Engineering

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy