International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / With recent improvements in data acquisition technology, it is now possible to use an FTI data acquisition system to measure analog signals with a total error from all sources of less than 0.05% - over an extended temperature range - and at high sample rates. This accuracy is better than one count of an old 10-bit system and includes non-linearities, initial errors (in gain, offset and excitation) and drift errors, simplifying the task of interpreting data acquisition system performance specifications. This paper looks at some practical steps taken to achieve this accuracy, from a hardware design and signal processing perspective. This leads to a discussion of implications for the FTI system designer, including: sensor and wiring specifications, sample rate, filtering specifications, and a discussion of implications for the data processing engineers.

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In an increasingly digital world, the need for high speed and high fidelity analog-to-digital (A/D) converters is paramount. Performance improvements in electronic A/Ds have not kept pace with demand, hence the need to consider alternative technologies. One such technology is photonics, as it takes advantage of optical sampling, high speed optical switches and low cross-talk interconnects. Optical sampling derives its advantage from the application of ultra low timing jitter (<100fs) mode locked lasers utilised to provide high speed clock pulses. In this thesis the feasibility and simulated performance of three different types of photonic oversampled A/D converters was investigated. The first, and simplest design is that of oversampled pulse-code-modulation (PCM), where a 2-level photonic comparator is used to sample the analog input at a frequency much greater than the Nyquist frequency. Subsequent low pass filtering produces a digital representation of the input. The other two architectures that were investigated are the first-order sigma-delta and error diffusion, which add one level of error correction to the PCM technique. These two architectures require the functional elements of a subtractor, comparator and delay. The photonic comparator and subtractor functionality was provided by Self-Electro-Optic Effect devices (SEED) based upon multiple quantum well (MQW) p-i-n devices. To facilitate calculation of the performance of the different architectures and aid in device design, a simulation of SEED operation based upon experimental data was developed. The simulation’s accuracy was demonstrated by agreement with the results from experimental S-SEED switching and optical subtraction. To emphasize the utility of the model, the simulation was subsequently used to demonstrate tristability of an S-SEED and critical slowing down in a bistable S-SEED. These effects were experimentally verified. To provide enhanced comparator contrast ratio and subtractor dynamic range, resonantly enhanced microcavity multiple quantum well (MQW) p-i-n devices were designed and grown by MOCVD. The operation of the subtractor and comparator was experimentally demonstrated and utilising temperature tuning, optimised performance was achieved with devices from the same wafer. Furthermore, the inclusion of gain was shown to improve the subtractor performance to that demanded by the sigma-delta. The constraints on each architecture imposed by the unipolar nature of the light intensity were derived and the sigma delta architecture was shown to be superior to the error diffusion for a photonic implementation. Using the numerical simulation based upon experimentally derived data, the entire sigma delta architecture was simulated to calculate the expected performance. The signal-to-quantisation-noise ratio (SQNR) was calculated as a function input amplitude and a peak SQNR of 54dB was obtained for an oversampling ratio of 100. / http://library.adelaide.edu.au/cgi-bin/Pwebrecon.cgi?BBID=1283979 / Thesis (Ph.D.) -- University of Adelaide, School of Chemistry and Physics, 2007

Analog Computing Arrays (ACAs) provide a computation system capable of performing a large number of multiply and add operations in an analog form. This system can therefore implement several computation algorithms that are currently realized using Digital Signal Processors (DSPs) who have an analogues accumulate and add functionality. DSPs are generally preferred for signal processing because they provide an environment that permits programmability once fabricated. ACA systems propose to offer similar functionality by providing a programmable and reconfigurable analog system. ACAs inherent parallelism and analog efficiency present several advantages over DSP implementations of the same systems. The computation power of an ACA system is directly proportional to the number of computing elements used in the system. Array size is limited by the number of computation elements that can be managed in an array. This number is continually growing and as a result, is permitting the realization of signal processing systems such as real-time speech recognition, image processing, and many other matrix like computation systems. This research provides a systematic process to implement, program, and use the computation elements in large-scale Analog Computing Arrays. This infrastructure facilitates the incorporation of ACA without the current headaches of programming large arrays of analog floating-gates from off-chip, currently using multiple power supplies, expensive FPGA controllers/computers, and custom Printed Circuit Board (PCB) systems. Proof of the flexibility and usefulness of ACAs has been demonstrated by the construction of two systems, an Analog Fourier Transform and a Vector Quantizer.

High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in a wide range of applications. High-speed, medium-resolution ADCs have been implemented by various ADC architectures such as a folding ADC, a subranging ADC, and a pipeline ADC. Among them, pipeline ADCs have proven to be efficient architectures for applications such as digital communication systems, data acquisition systems and video systems. Especially, power dissipation is a primary concern in applications requiring portability. Thus, the objective of this work is to design and build a low-voltage low-power medium-resolution (8-10bits) high-speed pipeline ADC in deep sub-micron CMOS technology. The non-idealities of the circuit realization are carefully investigated in order to identify the circuit requirements for a low power circuit design of a pipeline ADC. The resolution per stage plays an important role in determining overall power dissipation of a pipeline ADC. The pros and cons of both large and small number of bits per-stage are examined. A power optimization algorithm is developed to decide more accurately which approach is better for lower power dissipation. Both identical and non-identical number of bit per-stage approaches are considered and their differences are analyzed. A low-power, low-voltage 10-bit 100Msamples/s pipeline ADC was designed and implemented in a 0.18mm CMOS process. The power consumption was minimized with the right selection of the per-stage resolution based on the result of the power optimization algorithm and by the scaling down the sampling capacitor size in subsequent stages.

The goal of this research is to design a low power, high speed, 10-bit, 250 MHz digital-to-analog converter. For high speed application, the DAC is implemented in thermometer-code based segmented DAC. An optimal switching scheme is used in this design. The switching scheme can compensate the gradient error in thermometer-code DAC arrays.This DAC is implemented in a 0.18£gm 1P6M mixed-signal CMOS process provided by TSMC.

This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.

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