Thesis (M.A.)--Boston University / A method of reducing the graininess of a photographic print and increasing resolution in low contrast regions is described. The method involves the printing of more than one negative frame to produce one print. This requires a series of negatives with identical detail coverage in the area to be printed. The success of the method depends largely on the precision of the solution of the registration problem. Each negative is printed in turn, using the normal exposure, partitioned in as many parts as there are negatives to be printed. Each negative must be registered as exactly as possible in the image area. Four different aerial emulsions were used to obtain the 35-mm negatives for the superimposition printing technique. Kodak films used were: Tri X-RP Aercon, Super XX-RP Aerial Recon, Plus X Aerocon (SO 1166), and SO-1213. The exposure versus resolution characteristics and the basic sensitometric curves were developed for these films prior to exposure of the final series of negative frames. The negatives were exposed under identical conditions with the exception of lens openings and shutter speeds at an object to image ratio of 160 to 1. The camera was a Contax IIA with a 50-nm F/2 Sonnar lens. The camera exposure settings were: Tri-X, F/16, 1/250 second; Plus X, F/16, 1/100 second; SO-1213, F/11, 1/50 second. Due to the level of brightness of the target, the camera lens was not used at its best aperture. No filter was used. [TRUNCATED].

This thesis describes the development and testing of an analogue computer capable in principle of solving twentieth-degree polynomials with real coefficients, tenth-degree polynomials with complex coefficients, and of performing Fourier synthesis of even and odd functions as well as simulating system-function response curves. A description of the computer components and layout including all necessary power supplies is given. Emphasis is placed on the correct adjustment procedure. Results from illustrative problems verifying the computer operation are given. These results indicate that in favourable cases, accuracies of two significant figures for the modulus and of two degrees for the argument are obtainable for the zeros of a polynomial. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

This thesis explores the threshold between the analog and digital realms through various investigation of theories and methods. My interest in this subject came as a result when reflecting upon my 5 years at KTH, describing a gradual transition from analog to digital. This raised questions of the relevance of analog in an otherwise digital reality. The aim of this project was never defined in advance, instead a selection of questions and observations emerged as a result. The intension was never to declaim one or the other but rather to investigate in new possibilities connected to its use.

Electrocardiography (ECG) signal transmitter is the device used to transmit the electrical signals of the heart to the remote machine. These electrical signals are ECG signals caused due to electrical activities in the heart. ECG signals have very low amplitude and frequency; hence amplification of the signals is needed to strengthen the signal. Conversion of the amplified signal into digital information and transmitting that information without losing any data is the key. This information is further used in monitoring the heart.

In this dissertation we study a pioneering model of analog computation called General Purpose Analog Computer (GPAC), introduced by Shannon in 1941. The GPAC is capable of manipulating real-valued data streams. Its power is characterized by the class of differentially algebraic functions, which includes the solutions of initial value problems for ordinary differential equations. We address two limitations of this model. The first is its fundamental inability to reason about functions of more than one independent variable (the `time' variable). In particular, the Shannon GPAC cannot be used to specify solutions of partial differential equations. The second concerns the notion of approximability, a desirable property in computation over continuous spaces that is however absent in the GPAC. To overcome these limitations, we extend the class of data types by taking channels carrying information on a general complete metric space X; for example the class of continuous functions of one real variable. We consider the original modules in Shannon's construction (constants, adders, multipliers, integrators) and add two new modules: a differential module which computes spatial derivatives; and a continuous limit module which computes limits. We then build networks using X-stream channels and the abovementioned modules. This leads us to a framework in which the speci cations of such analog systems are given by fi xed points of certain operators on continuous data streams, as considered by Tucker and Zucker. We study the properties of these analog systems and their associated operators. We present a characterization which generalizes Shannon's results. We show that some non-differentially algebraic functions such as the gamma function are generable by our model. Finally, we attempt to relate our model of computation to the notion of tracking computability as studied by Tucker and Zucker. / Thesis / Doctor of Philosophy (PhD)

This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.

This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of the DAC error is indicated through a simple model for unit-element based DACs. The impact of the DAC error on the performance of ADC is then analyzed. Various techniques dealing with the DAC error are described and their drawbacks are pointed out. Based on the nature of the DAC error and the surrounding signals, a fully digital method to estimate the error from the ADC output and remove it is proposed. Simulation results are shown to support the effectiveness of the method. Simulations also show that the proposed technique can work together with the technique of adaptive compensation for quantization noise leakage in cascaded delta sigma (MASH) ADC cases. These two techniques are the foundation for the design of high speed, high resolution delta sigma ADCs with relaxed requirements on the analog circuits. To verify the proposed technique, an experimental MASH ADC was built, including the design and fabrication of a chip of a second-order multi-bit delta sigma ADC in a 1.6��m CMOS technology. The measured results show that the proposed DAC correction technique is highly effective. / Graduation date: 2004

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters (ADCs and DACs). Most delta-sigma modulators in production today employ single-bit quantization because a 1-bit DAC is inherently linear, whereas a multi-bit DAC is not. Were it not for this drawback, the use of multi-bit quantization would improve a delta-sigma modulator's performance by increasing the modulator's resolution or increasing the modulators's bandwidth, while at the same time whitening the quantization noise and improving modulator stability. This thesis explores the element-mismatch-shaping technique, which attenuates the noise caused by static element mismatch in a multi-level DAC by a method similar to delta-sigma modulation. Existing element-matching techniques are reviewed and some analytical and architectural work related to the realization of mismatch-shaping logic is presented. A custom switched-capacitor (SC) DAC is used to verify various element mismatch-shaping algorithms. Experiments show that mismatch-shaping can reduce harmonic distortion by up to 30 dB. / Graduation date: 1998

Thesis (Ph. D.)--Oregon State University, 2010. / Printout. Includes bibliographical references (leaves 74-75). Also available on the World Wide Web.

Thesis (Ph. D.)--University of Texas at Austin, 2003. / Supervisor: Jacob Abraham and Shouli Yan. Vita. Includes bibliographical references. Available also from UMI Company.