Hugh E. White. / "April 29, 1957." "This report is based on a thesis submitted to the Department of Electrical Engineering, M.I.T., April 30, 1957, in partial fulfillment of the requirements for the degree of Master of Science." / Bibliography: p. 28. / Army Signal Corps Contract DA36-039-sc-64637 Dept. of the Army Task 3-99-06-108 Project 3-99-00-100

E.J. Angelo, Jr. / "October 27, 1952." / Bibliography: p. 41. / Army Signal Corps Contract No. DA36-039 sc-100 Project No. 8-102B Dept. of the Army Project No. 3-99-10-022

Image smoothing and segmentation algorithms are frequently formulatedsas optimization problems. Linear and nonlinear (reciprocal) resistivesnetworks have solutions characterized by an extremum principle. Thus,sappropriately designed networks can automatically solve certainssmoothing and segmentation problems in robot vision. This papersconsiders switched linear resistive networks and nonlinear resistivesnetworks for such tasks. The latter network type is derived from thesformer via an intermediate stochastic formulation, and a new resultsrelating the solution sets of the two is given for the "zerostermperature'' limit. We then present simulation studies of severalscontinuation methods that can be gracefully implemented in analog VLSIsand that seem to give "good'' results for these non-convexsoptimization problems.

Marroquin and Ramirez (1990) have recently discovered a class of discrete stochastic cellular automata with Gibbsian invariant measures that have a non-reversible dynamic behavior. Practical applications include more powerful algorithms than the Metropolis algorithm to compute MRF models. In this paper we describe a large class of stochastic dynamical systems that has a Gibbs asymptotic distribution but does not satisfy reversibility. We characterize sufficient properties of a sub-class of stochastic differential equations in terms of the associated Fokker-Planck equation for the existence of an asymptotic probability distribution in the system of coordinates which is given. Practical implications include VLSI analog circuits to compute coupled MRF models.

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 106-110). Also available on the World Wide Web.

This thesis deals with the characterization, modeling and calibration of pipeline analog-digital converters (ADC)s. The integral nonlinearity (INL) is characterized, modeled and the model is used to design a post-correction block in order to compensate the imperfections of the ADC. The INL model is divided into: a dynamic term designed by the low code frequency (LCF) component depending on the output code k and the frequency under test m, and a static term known as high code frequency (HCF) component depending solely on the output code k. The HCF is related to the pipeline ADC circuitry. A set of adjacent piecewise linear segments is used to model the HCF. The LCF is the dynamic term depending on the input signal characteristics, and is modeled using a polynomial with frequency dependent coefficients. Two dynamic calibration methodologies are developed to compensate the imperfections of the pipeline ADC. In the first approach, the INL model at hand is transformed into a post-correction scheme. Regarding the HCF model, a set of gains and offsets is used to reconstruct the HCF segments structure. The LCF polynomial frequency dependent coefficients are used to design a bank of FIR filters which reconstructs the LCF model. A calibration block made by the combination of static gains/offsets and a bank of FIR filters is built to create the correction term to calibrate the ADC. In the second approach, the calibration (and modeling) process is extended to the upper Nyquist bands of the ADC. The HCF is used directly in calibration as a look-up-table (LUT). The LCF part is still represented by a frequency dependent polynomial of which the coefficients are used to develop a filter bank, implemented in the frequency domain with an overlap-and-add structure. In brief the calibration process is done by the combination of a static LUT and a bank of frequency domain filters. The maximum likelihood (ML) method is used to estimate the K-factor of a wireless Ricean channel. The K-factor is one of the main characteristics of a telecommunication channel. However, a closed-form ML estimator of the Kfactor is unfeasible due to the complexity of the Ricean pdf. In order to overcome this limitation, an approximation (for high K-factor values) is induced to the Ricean pdf. A closed-form approximate ML (AML) for the Ricean K-factor is computed. A bias study is performed on the AML and the bias derived value is used to improve the AML estimation, leading to a closed-form bias compensated estimator (BCE). The BCE performance (in terms of variance, bias and mean square error (MSE)) is simulated and compared to the best known closed-form moment-based estimator found in the literature. The BCE turns to have a superior performance for low number of samples and/or high K-factor values. Finally, the BCE is applied on real site wireless channel measurements in an urban macro cell area, using a 4-antenna transmit/receive MIMO system. / QC 20120528

In this thesis different aspects of general low power design and LNA-design have been studied. A new architecture for an ultra low power LNA is proposed and simple simulation results are presented. Simulations show that there should be possible to design a 2.4 GHz LNA that works sufficiently at 200 µA. The proposed architecture achieved a voltage gain over 20 dB from 2.32 to 2.5 GHz, a noise figure of 4.65 dB, IIP3 of -15.45 dBm and a input match of -9.5 dB. There is still a lot of work do and many simulations to perform before one can inconclusively conclude that the proposed architecture is a feasible solution, although the results generated in this thesis seem promising.

A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivator for using the SOI CMOS technology instead of bulk CMOS seems to be the smaller gate leakage power consumption. The targeted applications in mind for the ADCs are read channel and ultra wideband radio applications. These applications requires a resolution of at least four to six bits and a sampling frequency of above 1 GHz. Hence the flash ADC topology is chosen for the implementations. In this work we do also propose enhancements to the flash ADC converter. Further, this work also investigates introduction of dynamic element matching (DEM) into a flash ADC. A method to introduce DEM into the reference net of a flash ADC is proposed and evaluated. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a top-down design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level using MATLAB and SpectreHDL. The modeling results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC implementation has a conventional topology. It has a resistor net connected to a number of latched comparators and employs a ones-counter thermometer-to-binary decoder. This ADC serves as a reference for evaluating the other topologies. The measurements indicate a maximum sampling frequency of 470 MHz, an SNDR of 26.3 dB, and an SFDR of about 29 to 35 dB. The second ADC has a similar topology as the reference ADC, but its thermometer-to-binary decoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact decoder with a regular structure and a short critical path. The measurements show that it is more efficient in terms of power consumption than the ones-counter decoder and it has 40 % smaller chip area. Further, the SNDR and SFDR are similar as for the reference ADC, but its maximum sampling frequency is about 660 MHz. The third ADC demonstrates the introduction of DEM into the reference net of a flash ADC. Our proposed technique requires fewer switches in the reference net than other proposals. Our technique should thereby be able to operate at higher sampling and input frequencies than compared with the other proposals. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB in average when introducing DEM. The transistor level simulations in Cadence and measurements of the ADC with DEM indicates that the SFDR improves by 6 dB and 1.5 dB, respectively, when applying DEM. The smaller improvement indicated by the measurements is believed to be due to a design flaw discovered during the measurements. A mask layer for the resistors of the reference net is missing, which affects their accuracy and degrades the ADC performance. The same reference net is used in the other ADCs, and therefore degrades their performance as well. Hence the measured performance is significantly lower than indicated by the transistor level simulations. Further, it is observed that the improved SFDR is traded for an increased chip area and a reduction of the maximum sampling frequency. The DEM circuitry impose a 30 % larger chip area.

The main purpose of this thesis is to research High-Order Sigma-Delta Analog-to-Digital converter for precision measurement, a PI compensator and a third-order Sigma-Delta modulator has been proposed based on a second-order Sigma-Delta modulator. In accordance with the analysis result of frequency domain and time domain of system, we use third-order model because of better response with auxiliary software to simulate and implement the system, then measure modulator output variance for input variation. This converter circuit demonstrates that it can achieve the requirements of precision and linearity which the measure instrument demands.

The digital product increases widely and vastly. Because we live in the analog world, we require a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed and low power analog to digital converter. In this thesis, the circuits are designing with TSMC.18 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit.