This thesis proposes a systematic, hierarchical, optimization based semi-formal equivalence checking methodology for large analog/mixed signal systems such as phase locked loops (PLL), analog to digital convertors (ADC) and input/output (I/O) circuits. I propose to verify the equivalence between a behavioral model and its electrical implementation over a limited, but highly likely, input space defined as the Constrained Behavioral Input Space. Furthermore, I clearly distinguish between the behavioral and electrical domains and define mapping functions between the two domains to allow for calculation of deviation between the behavioral and electrical implementation. The verification problem is then formulated as an optimization problem which is solved by interfacing a sequential quadratic programming (SQP) based optimizer with commercial circuit simulation tools, such as CADENCE SPECTRE. The proposed methodology is then applied for equivalence checking of a PLL as a test case and results are shown which prove the correctness of the proposed methodology.

Det här arbetet handlar om att ta fram beteendemodeller av analog till digital omvandlare avsedda för tillämpningar i radiofrekvensområdet. Det gäller tillämpningar inom telekommunikation men även in test- och mätinstrument där omvandlingen från analoga till digitala signaler ofta är en prestandamässig flaskhals. Modellerna är avsedda att användas för att efterbehandla utdata från omvandlaren och på så sätt förbättra prestanda på den digitala signalen. Genom att skapa modeller av verkliga omvandlare och hur dessa avviker från ett idealt beteende kan ofullständigheter korrigeras genom så kallad postkorrigering. Beteendemodeller innebär att genererar en lämplig insignal, mäta utdata och beräkna en modell. För omvandlare i radiofrekvensområdet ställs höga krav på instrumentering. Den testutrustningen som används är baserad på moderna högprestanda instrument som har kompletterats med specialbyggd utrustning för signalkonditionering och datainsamling. I avhandlingen har även olika insignaler utvärderats med såväl teoretisk som experimentell analys. Det finns ett flertal olika varianter av modeller för att modulera ett olinjär, dynamisk system. För att få en parametereffektiv modell har utgångspunkten varit att utgå från en Volterramodell som på ett optimalt sätt beskriver svagt olinjära dynamiska system, så som analog till digital omvandlare, men som är alltför omfattande i antal parametrar. Volterramodellens har sedan reducerats till en mindre parameterintensiv, modellerstruktur på så sätt att Volterrakärnans symmetriegenskaper jämförts med symmetrierna hos andra modeller. En alternativ metod är att använda en Kautz-Volterramodell. Den har samma generella egenskaper som Volterramodellen, men är inte lika parameterkrävande. I den här avhandlingen redovisas experimentella resultat av Kautz-Volterramodellen som i framtiden kommer att vara intressanta att använda för postkorrigeringen. För att kunna beskriva beteenden som en dynamiska olinjära modellen inte klarar av har modellen kompletterats med en statisk styckvis linjär modellkomponent. I avhandlingen presenteras en sluten lösning för att identifiera samtliga paramervärden i modellen. Vidare har det i avhandlingen genomförs en analys av hur respektive komponent påverkar prestanda på utsignalen. Därigenom erhålls ett mått på den maximala prestandaförbättring som kan uppnås om felet kan elimineras. / This work considers behavior modeling of analog to digital converters with applications in the radio frequency range, including the field of telecommunication as well as test and measurement instrumentation, where the conversion from analog to digital signals often is a bottleneck in performance. The models are intended to post-process output data from the converter and thereby improve the performance of the digital signal. By building a model of practical converters and the way in which they deviate from ideal, imperfections can be corrected using post-correction methods. Behavior modeling implies generation of a suitable stimulus, capturing the output data, and characterizing a model. The demands on the test setup are high for converters in the radio frequency range. The test-bed used in this thesis is composed of commercial state-of-the-art instruments and components designed for signal conditioning and signal capture. Further, in this thesis, different stimuli are evaluated, theoretically as well as experimentally. There are a large number of available model structures for dynamic nonlinear systems. In order to achieve a parameter efficient model structure, a Volterra model was used as a starting-point, which can describe any weak nonlinear system with fading memory, such as analog to digital converters. However, it requires a large number of coefficients; for this reason the Volterra model was reduced to a model structure with fewer parameters, by comparing the symmetry properties of the Volterra kernels with the symmetries from other models. An alternative method is the Kautz-Volterra model, which has the same general properties as the Volterra model, but with fewer parameters. This thesis gives experimental results of the Kautz-Volterra model, which will be interesting to apply in a post-correction algorithm in the future. To cover behavior not explained by the dynamic nonlinear model, a complementary piecewise linear model component is added. In this thesis, a closed form solution to the estimation problem for both these model components is given. By gradually correcting for each component the performance will improve step by step. In this thesis, the relation between a given component and the performance of the converter is given, as well as potential for improvement of an optimal post-correction. / QC 20100629

As the rapid development of the wireless communication system and mobile video devices, the integrated chip with low power consuming and high conversion efficiency is widely needed. ADC and DAC are playing an important role in these applications. The aim of this thesis is to verify a post-correction method which is used for improving the performance of ADC. First of all, this report introduces the development and present status of ADC, and expatiate its important parameters from two different classes (static performance and dynamic performance). Based on the fundamental principle, the report then focuses on the dynamic integral non-linearity modeling of ADC. Refer to this model, one post-correction method is described and verified. Upon the face of post-correction, this method is to modify the output signals which have been converted from analog to digital format by adding a correction term. Improvement made by the post-correction needs to be checked out. Thus the performance analysis mainly relay on the measures of total harmonic distortion and signal to noise and distortion ratio is also included in this thesis.

Since digital system has become very common today it is important to have good interfaces in between the analog and digital domain. This puts high demandson the analog to digital converter. It is therefore important in the design of theanalog to digital converter to reduce noise and offset as much as possible. That isalso what this analysis is going to consider but in a comparator which is a crucialpart of the analog to digital converter. The comparator consists of a preamplifierand a latch and it is the preamplifier that will be studied here. The analog todigital converter in consider is of PSAR structure. Some other structures will alsobe mentioned in the first part together with some noise theory.

The Analog to Digital Converter (ADC) is an inevitable part of video AnalogFront Ends (AFE) found in the electronic displays today. The need to integratemore functionality on a single chip (there by shrinking area), poses great designchallenges in terms of achieving low power and desired accuracy.The thesis initially focuses upon selection of suitable Analog to Digital Converter(ADC) architecture for a high definition video analog front end. SuccessiveApproximation Register (SAR) ADC is the selected architecture as it scales downwith technology, has very less analog part and has minimal power consumption.In second phase a mathematical model of a Time-Interleaved Successive ApproximationRegister (TI-SAR) ADC is developed which emulates the behavior ofSAR ADC in Matlab and the errors that are characteristic of the time interleavedstructure are modeled.In the third phase a behavioral model of TI-SAR ADC having 16 channels and12 bit resolution, is built using the top-down methodology in Cadence simulationtool. All the modules were modeled at behavioral level in Verilog-A. The functionalityof the model is verified by simulation using signal of 30 MHz and clockfrequency of 300 MHz, using a supply voltage of 1.2 V. The desired SNDR (Signalto Noise Distortion ratio) 74 dB is achieved.In the final phase two architectures of comparators are implemented in 65nmtechnology at schematic level. Simulation results show that SNDR of 71 dB isachievable with a minimal power consumption of 169.6 μWper comparator runningat 300 MHz.NyckelordKeywords

The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance. The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture. The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.

This work documents the important design considerations and high--level development of an efficient Continuous-Time DS A/D converter for given system requirements. Projecting characteristics is especially essential in the design of the option-versatile DS converter and involves both advanced control and signaling theory, in addition to circuit and system design. Thus, extensive simulations were carried out through synthesis and behavioral modelling.Synthesis was performed using R. Schreiers DS toolbox while modelling was done using the framework of Cadence with Virtuoso and Spectre. Behavioral modelling was based on the mixed-signaling language VerilogA. A list of candidates, meeting the performance requirements set, were formed from synthesis and two modulator architectures stood out; a multi-bit third order and a single-bit fifth order, both with an oversampling ratio of 32. Both feedback and feedforward loop filter structures were analyzed.A useful and powerful analysis was carried out to characterize and quantify the impact of location on nonidealities in DS modulators. The model was prepared for verification, helping to analyze, characterize and specify crucial parts of each structure. Decisive nonidealities, such as excess loop delay, finite DC gain, limited GBW, circuit noise and their influence on the overall modulator were included and examined. From this, a specification for the integrators as well as a preliminary noise and power budget was established.The final result ends in a realistic environment capable of analyzing different types of CTDS structures and making an informed decision on the most optimal and suitable configuration. Results from synthesis and behavioral modelling showed a great correspondance between the results obtained in each part. After an iterative process of evaluating performance among other metrics with nonideal effects, the best architecture was found to be the third order multi-bit feedback modulator, which achieved all of the requirements while consuming 3724uW

The objective of this thesis was to design a power-efficient general purpose SAR ADC. The ADC's requirements were set by Energy Micro, favoring a very high performance-to-power ratio. The requirements are based on the present Energy Micro ADC, but with a 67% reduction in current consumption, a more modern CMOS technology of 90nm and a supply voltage of 1.2V.A full SAR ADC model was made using SPICE and VHDL code for the analog and digital sub-systems, respectively. The comparator was thoroughly designed and optimized, to achieve enough performance with as little power as possible. Then the total capacitor value of the sub-DAC was minimized, using extra reference voltages, minimizing the dynamic power consumption of the reference voltage generator. An asynchronous clock was also implemented, substantially increasing the available settling times of the comparator.The result was a very power-efficient SAR ADC, which fulfills the power-consumption requirement with 114$mu$J per conversion. Compared to other, similar SAR ADC's which has been researched, the ADC designed in this thesis is found to be very power-efficient. There might be some linearity problems in the ADC, partly from the transmission gates used as switches, but the overall design seems promising.

The low noise amplifier is a critical part of most high performance ultrasoundreceivers, and is important for achieving high sensitivity and a wide dynamic range.By having a large gain in the low noise amplifier, the total noise of the receiversystem will be dominated by that of the amplifier. For most low noise amplifier,there is a fundamental trade–off between accuracy and power consumption, whichmakes it difficult to design micro power front–end amplifiers with excellent noiseperformance. In some cases, however, lower accuracy can be tolerated if the sourceitself is noisy. This is the case for small, high impedance sources, where the noiselevel is in the region of 18 nV/sqrt{Hz}.This thesis presents the design and simulations of a low noise amplifier instandard 180 nm CMOS suitable for use with high impedance sources. In fact,high impedance sources pose challenges on the biasing of voltage amplifiers,where maintaining high input impedance is necessary. In addition, for differentialamplifiers, implementing common–mode feedback will typically result in a significantincrease in power consumption and area overhead. To alleviate this problem, aswitched common–mode feedback scheme is implemented, that also provide highinput impedance biasing of the input transistors.In order to cope with the large dynamic range requirement inherent in manyultrasound modalities, variable gain is often used to compress the dynamic rangefor the analog front–end. Methods for adding variable gain without resulting in alarge increase in area and power consumption is therefore of huge interest in manyultrasound applications. Several methods of adding variable gain is investigated inthis thesis, and a capacitive attenuator is proposed, which causes minimum increasein noise factor, while increasing the gain range by at least 20 dB.Large scale integration of several thousands analog front–ends in a singleultrasound probe handle requires low power consumption and minimum areaoverhead for all parts of the analog front–end, including the low noise amplifier.By using a figure–of–merit based optimization technique, the designed amplifiertopology achieves an low power consumption of 17.3 μA, while maintaining a noisefactor of less than 3 dB at resonance. In addition to performing a single–ended todifferential conversion, this amplifier realizes a maximum voltage gain of 23.4 dB,with a 3 dB bandwidth of 21.5 MHz.

This thesis presents an ultra-low-power 8-bit asynchronous current-modesuccessive approximation (SAR) ADC for single channel neuron spike recording.The novel design exploits current mode operating in weak inversion forhigh power efficiency and is designed to operate at a 1.8V supply. The ADC isrunning at a 16kHz sampling frequency using under 1uW of power, thoughis adjustable using the featured calibration registers. A finished layout ispresented, occupying less than 0.078mm2. Linear operation through mismatchand process variations is obtained using a current calibration circuitconnected to both the current mode DAC and all the biases. This ensuresINL < 0.5 and DNL < 1, yielding no missing codes and a 3sigma productionyield. Calibration is needed because of the relatively large mismatch causedby sub-threshold operation of the current mirrors. The design also offers anewly developed current comparator with high resolution and fast settlingrelative to the current level and is completable with other state-of-the-art solutions,though still feature some voltage scaling issues left for future work.