Les glycanes présents à la surface des cellules cancéreuses sont souvent modifiés par rapport à ceux d’une cellule saine. Or ces antigènes glucidiques n’induisent pas de réponse immune efficace. La GalNAc est le premier sucre fixé lors de la O-glycosylation de type mucine et ainsi ce sucre entre dans la composition de nombreux antigènes tumoraux. Le but de notre travail était de préparer des analogues synthétiques de la GalNAc susceptibles d’être incorporés à la surface de cellules cancéreuses et dans les mucines synthétisées par les tumeurs, afin d’augmenter la réponse immune vis-à-vis des glycanes tumoraux. Nous avons synthétisé chimiquement des analogues de la GalNAc afin de les tester in vitro en tant que substrats de la voie de « sauvetage » de la GalNAc chez les mammifères et donc d’enzymes impliquées dans cette voie : une kinase (GK2) et une UDP-pyrophosphorylase (AGX1) humaines. Les meilleurs candidats ont permis la synthèse de différents UDP-sucres et une GalNAc-transférase (ppGalNAc T1) bovine a pu être utilisée in vitro pour transférer certains de ces analogues, à partir de leur forme activée en UDP-sucre, sur des peptides. Nous avons donc pu montrer que certains des analogues synthétisés étaient capables de s’intégrer dans la voie de sauvetage et d’être incorporés dans des peptides. Le pouvoir immunologique des glycoconjugués de type mucine ainsi formés a été étudié chez la souris après couplage de ces glycoprotéines à une protéine immunostimulante (KLH). D’autre part, des cellules de mammifères ont également été cultivées en présence de ces analogues afin de vérifier leur incorporation au niveau des glycoconjugués de la surface des cellules. / Glycans are often present at the cancerous cell surface in a modified form compared to healthy cells. However, these carbohydrate antigens don’t lead to an effective immune response. GalNAc is the first sugar attached to mucin type O-glycans and is thus a component of numerous tumor antigens. The aim of our work was to prepare synthetic GalNAc analogs able to be incorporated at the surface of cancer cell and into mucins synthesized by tumors in order to increase the immune response toward tumor glycans. We chemically synthesized GalNAc analogs to test them in vitro as substrates of enzymes involved in the mammalian GalNAc salvage pathway: a human galactokinase (GK2) and a human UDP-pyrophosphorylase (AGX1). The best candidates allowed the synthesis of the corresponding UDP-sugars further used to test the transfer of those analogs onto peptides using a bovine GalNAc transferase (ppGalNAc T1). We have shown that some synthetic analogs could be integrated in the GalNAc salvage pathway and O-linked to peptides. Immunological properties of the glycoconjugates thus formed were studied in mice after coupling to an immunostimulant protein (KLH). Moreover, mammalian cells were cultivated in the presence of these analogs in order to check their incorporation into glycoconjugates at the cell surface.

Typescript (photocopy). / Digitized by Kansas State University Libraries

During the thesis, a two-staged analog baseband circuit incorporating a passive analog filter and a wideband voltage amplifier were successfully designed, implemented in an IC mask layout in a 65nm CMOS technology, and joined with a previously designed analog front-end design to form a wideband observation receiver. The baseband circuit is capable of receiving an IF bandwidth up to 990MHz produced by the analog front-end using low-side injection. The final circuit shows high IMD3 of at least 90 dBc. The voltage amplifier delivers a voltage amplification of 15 dB with around 0.08 dB amplitude precision over the bandwidth, while the passive filter is capable of a passband amplitude precision of 0.67 dB over the bandwidth, while effectively suppress signal images created by the mixer with at least 60 dBc. Both stages were realized in an IC mask layout, in addition, the filter layout were simulated using an EM simulator.

Syftet med denna litteraturstudie är att ge en bild av hur matematikdidaktisk forskning beskriver elevers förståelse för den analoga respektive digitala klockan i grundskolans tidigare år. För att ta reda på detta kommer följande frågeställningar användas: vilka svårigheter och missuppfattningar kan elever visa i sin förståelse för den analoga respektive digitala klockan? Vilka arbetssätt och metoder har visat sig kunna utveckla elevers lärande om klockan i undervisning? Studien har baserats på vetenskapliga artiklar som funnits via en systematisk sökprocess i olika databaser och kedjesökning. I studien konstateras att forskare lyfter fram olika arbetsmetoder i undervisning rörande klockan, men även likheter finns. Vi har sett att elevers mognad spelar en viktig roll när det kommer till undervisning om klockan, men hur undervisningen ska bedrivas kan dock se olika ut. Vi presenterar även forskarnas syn på vilka vanliga svårigheter och missuppfattningar som elever kan visa när de ställs inför analog eller digital representation av tid. Exempelvis är timvisaren och minutvisaren något som elever vanligtvis har svårt att särskilja. Vidare är forskarna eniga om att elever har lättare att förstå och avläsa den digitala klockan jämfört med den analoga.

Thesis advisor: Mary F. Roberts / Thesis advisor: Eranthie Weerapana / Small molecules are of interest both as metabolites in tumor cell biology and as potential therapeutics in the fight against cancer. In this work, small molecules in both roles have been examined. Modulation of tumor cell metabolism holds promise as a strategy to combat cancer, and both glucose and glutamine have been identified as critical fuels for tumor cell growth and proliferation. However, the reason for glutamine addiction is poorly understood. The differential metabolism of glutamine and glucose was therefore examined using ¹³C labeling and NMR-based metabolomics in the VM-M3 tumor cell line, which requires both glucose and glutamine for survival and proliferation. In the course of this study, a novel mammalian metabolite itaconic acid was identified. Itaconic acid was detected in extracts and tissue culture media from the murine macrophage-derived tumor cell lines VM-M3 and RAW 264.7 as well as in primary macrophages. Production and secretion of itaconic acid was increased upon stimulation. LC-MS and NMR based metabolomics studies show that this metabolite is synthesized by the decarboxylation of cis-aconitate from the TCA cycle, and provided evidence for a novel mammalian homologue of the enzyme cis-aconitic decarboxylase. D-3-deoxy diC₈PI is a small molecule of interest as a potential cancer therapeutic. This compound was designed to induce apoptosis in tumor cells by competitively binding to the Akt PH domain and preventing Akt translocation. However, high resolution ³¹P field-cycling studies show that both D-3-deoxy diC₈PI and an inactive analogue L-3,5-dideoxy diC₈PI bind to the same site on the PH domain, which is distinct from the binding site of the ligand diC₈PI(3,4,5)P₃. This makes the aforementioned mechanism of cytotoxicity unlikely. Aggregation of the PH domain in the presence of soluble headgroup IP₆ was also observed, which may be related to a physiological function of this protein and invalidates at least one other binding assay. Investigation into alterations in signaling pathways in the MCF-7 breast cancer cell line showed that D-3-deoxy diC₈PI activates the p38MAPK pathway which results in CREB hyperphosphorylation. However, activation of this pathway appears to be compensatory and unrelated to the mechanism of action. D-3-deoxy diC₈PI also decreases levels of cyclin D1 and cyclin D3, which regulate the progression of the cell cycle. These decreases appear to be occurring at the transcriptional level rather than due to increased proteasomal degradation. The loss of these two proteins does not cause apoptosis in MCF-7 cells, but siRNA knockdown of specifically cyclin D1 inhibits proliferation. This is consistent with the cell cycle arrest observed upon D-3-deoxy diC₈PI treatment in these cells. These findings do not conclusively elucidate the mechanism of cytotoxicity of D-3-deoxy diC₈PI, but provide a characterization of some of its effects in the MCF-7 cell line which may be useful for further studies. / Thesis (PhD) — Boston College, 2012. / Submitted to: Boston College. Graduate School of Arts and Sciences. / Discipline: Chemistry.

Au cours des dernières décennies, l’industrie de la micro-électronique a connu une large démocratisation de l’utilisation des applications de télécommunication. L’amélioration des procédés de conception et de fabrication ont permis de produire des circuits analogiques, mixtes et radiofréquences complexes et hautes performances pour ces applications. Toutefois, le coût de test de ces circuits intégrés représente encore une large part du coût de fabrication. En effet, très souvent, tester des fonctions analogiques ne se résume pas à un test fonctionnel mais signifie mesurer les spécifications du circuit. Ces mesures nécessitent l’utilisation d’instruments dédiés bien plus couteux que les ressources numériques disponibles sur un équipement de test industriel standard. Une des spécifications essentielle mais couteuse à caractériser pour les circuits RF est le niveau de bruit de phase. La technique actuellement utilisée en industrie consiste à capturer le signal à l’aide d’un canal testeur analogique équipé d’un convertisseur analogique-numérique hautes performances ; une transformée de Fourier est alors appliquée sur le signal numérisé et le bruit de phase est mesuré sur le spectre résultant. L’approche proposée dans cette thèse consiste à réaliser la mesure de bruit de phase en n’utilisant que des ressources digitales faible coût. L’idée fondamentale consiste à réaliser la capture 1-bit du signal analogique avec un canal numérique standard et à développer des algorithmes de post-traitement dédiés permettant de retrouver l’information relative au bruit de phase à partir d’une évaluation des temps de passages à zéro du signal. Deux méthodes sont présentées. La première méthode est basée sur une estimation de la fréquence instantanée du signal et une analyse de la dispersion induite par le bruit de phase. Cette méthode impose une contrainte forte quant à la fréquence d’échantillonnage à utiliser et s’est révélée sensible au bruit d’amplitude, limitant la gamme de mesures possibles. Une seconde méthode est alors proposée afin de s’affranchir de ces limitations. A partir de la capture binaire du signal analogique, une reconstruction de la phase instantanée du signal est réalisée, puis filtrée puis caractérisée grâce à un outil usuel d’évaluation de stabilité fréquentielle : la variance d’Allan. Cette technique, robuste au bruit d’amplitude et au jitter, peut être paramétrée et permet une caractérisation efficace du bruit de phase sans contrainte fondamentale. En plus des simulations, ces techniques font l‘objet d’une étude stochastique et sont validées expérimentalement sur différents types de signaux à mesurer – générés artificiellement ou provenant de puces sur le marché – et avec différentes conditions mesures – sur oscilloscope ou sur testeur industriel, en laboratoire et en production –. Une implémentation sur puce est aussi proposée et validée avec un prototype sur FPGA. / In recent decades, the microelectronics industry has experienced a wide democratization of the use of telecommunication applications. The improved process design and manufacturing have produced complex and high performance analog, mixed and radio frequency circuits for these applications. However, the test cost of these integrated circuits still represents a large part of the manufacturing cost. Indeed, very often, analog testing is not just a functional test but needs measurements for specification validations. These measurements require the use of dedicated instruments expensive resources on standard industrial test equipment.One of the essential but costly specifications to validate in RF circuitry is the phase noise level. The currently used industrial technique consists in capturing the signal from the circuit under test using an RF tester channel equipped with a high performance analog to digital converter; a Fourier transform is then applied to the digitized signal and the phase noise is measured on the resulting spectrum.The approach proposed in this thesis is to achieve the phase noise measurement using solely digital low-cost resources. The basic idea is to perform 1-bit capture of the analog signal with a standard digital channel and develop post-processing algorithms dedicated for phase noise evaluation from the zero-crossings of the signal.Two methods are presented. The first method is based on an estimate of the instantaneous signal frequency and an analysis of their dispersion induced by phase noise. This method imposes a strong constraint on the sampling frequency to be used and proved to be sensitive to noise amplitude, limiting the range of possible measures. A second method is then proposed to overcome these limitations. From the binary capture of the analog signal, a reconstruction of the instantaneous phase of the signal is carried out, then filtered and characterized by a common tool of frequency stability assessment: the Allan variance. This technique, robust to amplitude noise and jitter, can be parametrized and enables efficient characterization of phase noise without fundamental constraint.In addition to the simulations, these techniques are subject to a stochastic study and are validated experimentally on different types of signals to be measured - artificially generated or from chips on the market - and with different measuring instruments - on oscilloscope or industrial tester, in laboratory and on a production line-. An On-chip implementation is also proposed and validated with a FPGA prototype.

Tang, Xian. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

在過去的十年裡，隨著便攜式通訊，電腦與消費電子市場的快速發展，以及在超大規模積體電路中，越來越多的功能實現被轉移到數字領域中，這些都引起了人們對模數轉換器研究的極大關注。 / 基於過採樣與量化誤差整形技術，ΣΔ模數轉換器對與類比電路中的非理想特性具有很強的容忍度。然而，爲了優化其在功耗，硅片面積與上市時間等方面的性能，ΣΔ模數轉換器的設計需要對眾多實際問題做出折中考慮。本文在不同的設計層次上提出了一些創新，包括算法，架構及電路設計，從而提升其在通訊，語音與傳感等應用領域中的性能指標。 / 本文第一部份提出的新技術主要解決運用於低中頻無線接收器中開關電容型正交帶通ΣΔ模數轉換器的I/Q通道的不匹配問題。這些I/Q通道的不匹配將導致位於臨近信道的鏡像信號，自鏡像信號及量化噪聲混疊至輸入信道，從而降低模數轉換器的動態範圍。為此，本文提出了一種新的動態單元匹配技術與一種雙線性技術來解決上述問題。同時通過在I/Q信道間複用運算放大器，比較器與數模轉換器，芯片的面積得到了大幅的降低。基於以上技術，在0.18微米CMOS工藝上設計實現了開關電容型正交帶通ΣΔ模數轉換器的測試樣片，其鏡像抑制比可達到73dB，這是迄今為止公開發表論文中報告的最高值。 / 在本文的第二部份，我們關注ΣΔ模數轉換器在音頻領域的應用。其對動態範圍與功耗提出的較高要求為級聯型連續時間ΣΔ模數轉換器帶來了機遇。然而，相比于單環型，級聯型連續時間ΣΔ模數轉換器對於電阻-電容時間常數的偏離及有限的運放低頻增益等非理想特性表現得更加敏感，因為這些不理想因素將影響量化噪聲在模擬與數字路徑中的精確抵消。為此，我們提出了使用脈寬調製技術來對片上的電阻-電容時間常數進行自動調整。基於脈寬調製技術，我們可以使用在離散時間電路中常用的相關雙採樣技術來提高運放的有效低頻增益。同時我們提出了一種有限運放帶寬補償技術來節省芯片的功耗。另外，本文對基於連續時間ΣΔ模數轉換器的脈寬調製技術，相關雙採用技術，反混疊濾波，噪聲與抖動效應等方面均做出了詳盡的仿真與分析。最後我們對一顆基於0.18微米CMOS工藝設計的樣片進行了測試。測試結果表明，採用本文提出的技術可以將ΣΔ模數轉換器的動態範圍提高28dB以上。 / 本文的第三部份展示了一種可用於單端或差分電容傳感器的高精度電容-數字轉換器。在傳統的電容-數字轉換器中，由電容底板開關引入的電荷注入與數字輸出結果及被感知電容的容值有關。當被感知電容的容值變化範圍較大時，這些電荷注入將產生很大的非線性。對此本文提出了一種新的開關控制與校準算法。我們對一顆基於0.18微米CMOS工藝設計的二階電容-數字轉換器樣片進行了測試。測試結果表明，其在0.5毫秒的測試時間內可達到53.2aFrms的精度。同時本文提出的技術可以在0.5pF至3.5pF的較寬電容範圍內，使得電容-數字轉換器在單端電容傳感模式下的線性度（準確度）從9.3位提高至12.3位；在差分電容傳感模式下的線性度（準確度）從10.1位提高至13.3位。最後，本文對連接微機電電容型壓力傳感器和加速度傳感器的實際應用情境進行了測試。 / The rapid growth of the market for portable, battery operated systems for communications, computer and consumer electronics (3C), and the trend of moving functionality to the digital domain in very large scale integration (VLSI) systems have resulted in an enormously increasing interest in analog-to-digital converter (ADC) design. / Combining both oversampling and quantization error shaping techniques, delta sigma (ΔΣ) ADCs achieve a high degree of insensitivity to analog circuit imperfections. Nevertheless, the design of CMOS ΔΣ ADCs involves a number of practical issues and trade-offs that must be taken into account in order to optimize their performance in terms of power consumption, silicon area, and time-to-market deployment. This thesis proposes a number of novel performance-enhancement techniques on different design levels, including algorithm, architecture and circuit level, for ΔΣ ADCs in various application circumstances, such as telecom, audio, sensor, and so on. / First, novel techniques are proposed to mitigate I/Q mismatches in switched-capacitor quadrature bandpass Delta-Sigma modulators (DSMs) used in low-IF wireless receivers. The I/Q mismatches result in a nearby channel at the image frequency, the mirrored image of the desired signal around its center frequency (self-image) and the quantization noise to corrupt the desired signal, degrading the dynamic range of the modulator. A dynamic element matching scheme and a bilinear scheme are the proposed solution to reduce all the above-mentioned I/Q mismatch effects. Furthermore, a multiplexing scheme for the sharing of op-amps, quantizers and DACs between the I and Q channels is investigated for smaller chip area. A prototyping DSM was designed and fabricated in a 0.18 ưm CMOS, measuring an image rejection ratio of 73 dB, being the best reported. / Second, a pulse-width-modulation (PWM) technique is proposed for on-chip automatic RC time constant tuning for cascaded continuous-time (CT) DSMs for audio application. The demand for high signal-to-noise-plus-distortion ratio (SNDR) and low power brings a wealth of opportunities to the CT DSMs. In CT DSMs, cascading low-order stages provides an effective way to achieve stable high-order modulation. However, compared to CT single-loop modulators, CT cascaded modulators are more sensitive to variation of RC time constant and finite dc gain of the opamps as these nonidealities affect the precise cancellation of the quantization noises between the analog and digital paths. In the CT cascaded modulator presented here, we propose to apply a PWM technique for on-chip automatic RC time constant tuning. The application of PWM in turn enables the use of the correlated double sampling (CDS) technique, which is conventionally confined to discrete-time circuits, to boost the effective dc gain. The PWM further allows the use of a finite-opamp-bandwidth compensation technique for power saving. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented and verified with extensive simulations. Measurement results on a prototype CT cascaded 2-2 DSM in a 0.18ưm CMOS show that the proposed techniques can improve the dynamic range (DR), SNDR and spurious-free dynamic range (SFDR) of the modulator by at least 28 dB. / Third, a high-precision capacitance-to-digital converter (CDC) is proposed, which can be configured to interface with single-ended or differential capacitive sensors. In the conventional CDC, charge injection from bottom-plate switches depends on the digital output and the value of the sensing capacitor. Nonlinearity is resulted especially when the varying ranging of the sensing capacitor is wide. In this thesis, new switching and calibration schemes are proposed to reduce these charge injection. A prototyping 2nd order CDC employing the proposed techniques is fabricated in a 0.18ưm CMOS process and achieves a 53.2aFrms resolution in a 0.5ms measuring time. The proposed techniques improve the CDC's linearity from 9.3 bits to 12.3 bits in the single-ended sensing mode, and from 10.1 bits to 13.3 bits in the differential sensing mode, with a wide sensing capacitor range from 0.5 to 3.5pF. The CDC is also demonstrated with real-life pressure (single-ended) and acceleration (differential) sensors. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Li, Bing. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese. / Abstracts of thesis entitled: --- p.I / 摘 要 --- p.V / Contents --- p.VII / List of Figures --- p.XI / List of Tables --- p.XVI / Acknowledgement --- p.XVII / Chapter CHAPTER 1. --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Original contributions and outline of the thesis --- p.2 / References --- p.1 / Chapter CHAPTER 2. --- A High Image-Rejection SC Quadrature Bandpass DSM for Low-IF Receivers --- p.3 / Chapter 2.1 --- Mismatch in Complex Gain Blocks --- p.6 / Chapter 2.2 --- Mismatches in QBDSM --- p.8 / Chapter 2.3 --- Proposed High Image-Rejection QBDSM --- p.13 / Chapter 2.3.1 --- Technique to remove I/Q mismatches in the first complex resonator (for P1 in Fig. 2.6) --- p.13 / Chapter 2.3.2 --- Technique to remove I/Q mismatches in the Feedback DAC (for B in Fig. 2.6) --- p.19 / Chapter 2.3.3 --- Technique to remove I/Q mismatches in the Input Coefficient (for A1 in Fig. 2.6) --- p.20 / Chapter 2.3.4 --- Summary and Simulation Results --- p.27 / Chapter 2.4 --- I/Q Multiplexing Schemes and Circuit Implementation of the QBDSM --- p.34 / Chapter 2.5 --- Measurement Results Analysis --- p.40 / Chapter 2.6 --- Conclusions --- p.47 / Chapter APPENDIX I: --- I/Q MISMATCHES IN LOW-IF RECEIVERS --- p.48 / Chapter A. --- I/Q Mismatch in Mixer --- p.48 / Chapter B. --- I/Q Mismatch in Polyphase Filter --- p.49 / Chapter C. --- I/Q Mismatch in QBDSM --- p.50 / Chapter D. --- I/Q Imbalance Analysis for whole receiver --- p.51 / Chapter APPENDIX II: --- IRR Measurement Method --- p.52 / References --- p.56 / Chapter CHAPTER 3. --- A Continuous-time Cascaded Delta-Sigma Modulator with PWM-Based Automatic RC Time Constant Tuning and Correlated Double Sampling --- p.59 / Chapter 3.1 --- PWM for on-chip RC Time Constant Tuning --- p.61 / Chapter 3.1.1 --- Integrator Gain Error --- p.64 / Chapter 3.1.2 --- Automatic Generation of PWM Clock --- p.65 / Chapter 3.1.3 --- Modulator Architecture --- p.66 / Chapter 3.1.4 --- Anti-aliasing Filtering --- p.68 / Chapter 3.1.5 --- Noise Analysis --- p.69 / Chapter 3.2 --- Proposed SRMC Integrator with CDS --- p.71 / Chapter 3.2.1 --- Analysis on the opamp gain enhancement --- p.73 / Chapter 3.2.2 --- Simulation Results --- p.75 / Chapter 3.3 --- Compensation for Finite-Opamp-Bandwidth-Induced Error --- p.76 / Chapter 3.3.1 --- Compensation for fininte opamp bandwidth --- p.77 / Chapter 3.3.2 --- Behavorial Simulation Results --- p.79 / Chapter 3.4 --- Jitter Analysis --- p.80 / Chapter 3.4.1 --- Jitter on Rising Edges --- p.81 / Chapter 3.4.2 --- Duty cycle jitter --- p.84 / Chapter 3.5 --- Prototyping Modulator Design --- p.85 / Chapter 3.6 --- Measurement Results --- p.89 / Chapter 3.7 --- Summary --- p.95 / References --- p.97 / Chapter CHAPTER 4. --- A High-Linearity Capacitance to Digital Converter with Techniques Suppressing Charge Injection from Bottom-Plate Switches --- p.105 / Chapter 4.1 --- Introduction --- p.105 / Chapter 4.2 --- Proposed CDC Switching and Calibration Schemes --- p.107 / Chapter 4.2.1 --- Single-Ended Sensing Mode --- p.107 / Chapter 4.2.2 --- Differential Sensing Mode --- p.111 / Chapter 4.3 --- Circuit Implementation --- p.114 / Chapter 4.4 --- Measurement Results --- p.117 / Chapter 4.5 --- Conclusion --- p.125 / Chapter APPENDIX: The cross section of NPN transistor in triple-well CMOS process --- p.126 / References --- p.127 / Chapter CHAPTER 5. --- Conclusions and future works --- p.129 / Chapter 5.1 --- Conclusions --- p.129 / Chapter 5.2 --- Future works --- p.130 / Chapter APPENDIX: --- A typical CMOS fabrication process flow (1 poly/2 M, twin well CMOS) --- p.131

With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI.

Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the“Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the“Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within ±1 LSB.