A relatively new area of analog integrated circuits is emerging which is likely to have an impact on the signal processing area --analog floating-gate circuits. Analog floating- gate circuits have the potential to deliver more sophisticated signal processing at less power in a smaller space. This is the result of a novel application of digital memory technology -- the floating-gate MOSFET, that is used as an analog memory and computational device. Critical to the success of analog floating-gate circuits is on-chip programming. After investigating integrated schemes for DC-DC converters to generate the necessary voltages on chip, this research focuses on charge pumps that are integrated into the programming structure of floating-gate circuits. The impact of this research is far reaching since programmability is an indispensable feature of analog floating-gate circuits. This research lays the foundation for meeting the requirement of on-chip programming. Charge pumps will eliminate the need for high voltages to be externally supplied or regulated for analog floating-gate circuits. To the design engineer, the utilization of floating-gate circuits will look identical to their non floating-gate counterparts in terms of the value and number of supply voltages. In addition, the integration of on-chip DC-DC converters will reduce pin count, reduce board space for the implementation of the chip and facilitate distributed on chip power supplies for mixed signal integrated circuits.

This research focuses on biologically inspired audio signal processing using programmable analog circuitry. This research is inspired by the biology of the human cochlea since biology far outperforms any engineered system at converting audio signals into meaningful electrical signals. The human cochlea efficiently decomposes any sound into the respective frequency components by harnessing the resonance nature of the basilar membrane, essentially forming a bank of bandpass filters. In a similar fashion, this work revolves around developing a filter bank composed of continuous-time, low-power, analog bandpass filters that serve as the core front end to this silicon audio-processing system. Like biology, the individual bandpass filters are tuned to have narrow bandwidths, moderate amounts of resonance, and exponentially spaced center frequencies. This audio front end serves to efficiently convert incoming sounds into information useful to subsequent signal-processing elements, and it does so by performing a frequency decomposition of the waveform with extremely low-power consumption and real-time operation. To overcome mismatch and offsets inherent in CMOS processes, floating-gate transistors are used to precisely tune the time constants in the filters and to allow programmability of analog components.

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

This work considers alternative strategies to mainstream digital approaches to signal processing - namely analog and neuromorphic solutions, for increased computing efficiency. In the context of a speech recognizer application, we use low-power analog approaches for the signal conditioning and basic auditory feature extraction, while using a neuromorphic IC for building a dendritic classifier that can be used as a low-power word spotter. In doing so, this work also aspires to posit the significance of dendrites in neural computation.

Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and manufacturing variations, timing skews occur between the sampling clocks of the sub ADCs within the TI-ADC. These timing skews compromise the spurious free dynamic range of the converter. In addition, jitter on the sampling clocks, degrades the signal-to-noise ratio of the TI-ADC. Therefore, in order to maintain an acceptable spurious free dynamic range and signal to noise ratio, it is necessary to correct the timing skews while adding minimal jitter. Two analog-based architectures for correcting timing skews were investigated, with one being selected for implementation. The selected architecture and additional test circuitry were designed and fabricated in a 0.18??m CMOS process and tested using a 125 MSPS 16 bit ADC. The circuit achieves a correction precision on the order of 10???s of femtoseconds for timing skews as large as approximately 180 picoseconds, while adding less than 200 femtoseconds of rms jitter.

Auf dem Gebiet der Flugnavigation hat die Darstellung raumbezogener Information traditionell eine herausragende Bedeutung ...

Thesis (Ph. D.)--Ohio University, November, 1994. / Title from PDF t.p.

Thesis (Ph. D.)--University of Washington, 2007. / Vita. Includes bibliographical references (leaves 102-106).

Thesis (Ph. D.)--Carleton University, 2001. / Includes bibliographical references (p. 296-303). Also available in electronic format on the Internet.

Nürnberg, University, Diss., 2004--Erlangen.