Doctor of Philosophy / Department of Electrical and Computer Engineering / Behrooz Mirafzal / Corrective schemes for facilitating continued operation of dc-ac converters during internal and external abnormalities are presented in this dissertation. While some of the developed techniques are suited for any dc-ac converter topology, most of the presented methodologies are designed specifically for cascaded H-bridge (CHB) multilevel converters. While CHB provide increased scalability and efficiency compared to traditional topologies, these converters are more likely to experience internal faults due to the additional components required. Realizing the full potential of CHB converters requires fault tolerant techniques, such as those demonstrated in this dissertation. Adaptive sinusoidal pulse width modulation (ASPWM) is introduced in this dissertation as a method which enables CHB to directly utilize time-variant dc sources, increasing CHB flexibility when compared to traditional pulse width modulation (PWM) methods which require dc sources with equal magnitudes or with magnitudes existing in specific ratios. Two alternative algorithms are presented to enable ASPWM implementation, providing a trade off between system performance and required sensor circuitry. This dissertation also introduces a load independent analytical approach for identifying discordant operating points, i.e. operating points where some cells in an asymmetric CHB leg regenerate power while the overall leg delivers power, or vice-versa. Identification of these points is essential due to the deleterious effects which can result from extended discordant operation, for instance overcharging of batteries leading to lifespan degradation or even catastrophic failures such as fires or explosions. Additionally, a method for rapidly identifying, isolating, and verifying internal IGBT open-circuit and gate-driver faults is presented in this dissertation to address the increased probability of switch failures occurring within CHB. The proposed approach enables converter operation to continue in the event of gate-driver or open-circuit faults, but avoids unnecessary converter reconfiguration due to gate-misfiring faults. For a CHB leg with M cells, the proposed technique identifies and isolates open-circuit switch faults in less than 2M measurement (sampling) cycles, and verification is completed in less than one full fundamental cycle. Furthermore, this dissertation introduces a real-time implementable atypical PWM technique which enables increased dc bus utilization under a wide range of non-ideal operating conditions. While this approach is suitable for a wide range of converters operating under external abnormalities, for instance maximizing dc bus utilization for converters providing auxiliary services such as negative-sequence compensation, this approach also facilitates operation of CHB with faulty cells. The proposed method can be used with any control technique and any carrier-based PWM method, enabling its implementation in both symmetric and asymmetric CHB. In addition to these fault tolerant techniques, a novel approach for analyzing the active- and reactive-power deliverable by grid-interactive converters is proposed. This method facilitates performance comparisons for various converter configurations, simplifying the process for selecting filter components, dc bus voltages, and other system parameters. This analytical approach also enables converter performance to be analyzed during internal and external fault events, allowing assessment of converter robustness. The efficacy of the developed techniques are supported by MATLAB/Simulink simulations as well as experimental data obtained using a laboratory-scale cascaded H-bridge multilevel converter.

Wireless communication systems are based on frequency synthesizers that generate carrier signals, which are used to transmit information. Frequency synthesizers use voltage controlled oscillators (VCO) to produce the required frequencies within a specified period of time. In the process of generating frequency, the VCO and other electronic components such as amplifiers produce some unwanted short-term frequency variations, which cause frequency instability within the frequency of interest known as phase noise (PN). PN has a negative impact on the performance of the overall wireless communication system. A literature study conducted on this research reveals that the existing PN cancellation techniques have some limitations and drawbacks that require further attention. A new PN correction technique based on the combination of least mean square (LMS) adaptive filtering and single-loop single-bit Sigma Delta (SD) modulator is proposed. The new design is also based on the Cascaded Resonator Feedback (CRFB) architecture. The noise transfer function (NTF) of the architecture was formulated in way that made it possible to stabilize the frequency fluctuations within the in-band (frequency of interest) by locating its poles and zeros within the unit circle. The new design was simulated and tested on a commercially available software tool called Agilent Advanced Design System (ADS). Simulation results show that the new technique achieves better results when compared with existing techniques as it achieves a 104 dB signal-to-noise (SNR), which is an improvement of 9 dB when compared with the existing technique accessed from the latest publications. The new design also achieves a clean signal with minimal spurious tones within the inband with a phase noise level of -141 dBc/Hz (lower phase noise level by 28 dBc/Hz) when compared with the existing techniques. / Thesis (MEng)--University of Pretoria, 2017. / Electrical, Electronic and Computer Engineering / MEng / Unrestricted

Cascaded H-bridge (CHB) multilevel inverters have significant popularity with motor drives applications due to their modularity, scalability, and reliability. Typical CHB inverters employ diode rectifiers that allow unidirectional power flow from the grid to the load. To capture and utilize the regenerated energy in regenerative applications, regenerative CHB drives were introduced with two-level voltage source converters in the front end to allow bidirectional energy flow. This solution is accompanied by challenges of high number of switches and control circuits, high switching power losses, and massive dimensions. Recently, developing more economic versions of regenerative cascaded H-bridge drives has become one of the hottest topics in power electronics research. In this thesis work, two solutions are proposed for more energy efficient and economic regenerative CHB drives. The first solution is a proposed power cell configuration that reduces the number of switches per cell by two. Additionally, phase alternation connection method and carrier phase-shifting techniques are introduced to address the challenges of the presented configuration. The switch-count reduction reduces the system’s complexity, switches’ cost, and footprint. The second proposed solution is a new controller to operate the front-end converters as fundamental frequency ends (FFEs). The proposed controller is employed in both the conventional regenerative cascaded H-bridge and the proposed reduced switch-count configuration. This solution minimizes the switching power losses, and results in more compact and economic design, with higher DC-link utilization. Theoretical analysis and simulation studies of both proposed solutions show promising performance and capability to be applied as energy-efficient and cost effective regenerative CHB motor drives. Experimental validation of the proposed reduced switch-count configuration is presented for STATCOM operation of a scaled-down 7-Level regenerative CHB drive system. The future work of this thesis includes experimental validation of the proposed FFE controller, and operation of the system with regenerative motor load. / Thesis / Master of Applied Science (MASc)

High power converters are widely used in many industries. At power levels in the range of Mega Watt (MW), power conversion at medium voltage (MV) is preferred due to better efficiency and lower cost. For medium voltages applications, multilevel converters are widely adopted due to the features they offer with respect to two-level converters. Cascaded H-bridge topology is a widely adopted multilevel topology because of its modularity, scalability, and reliability. The conventional cascaded H-bridge topology allows two-quadrant operation. In order to allow fourquadrant operation, an active front end version of the cascaded H-bridge topology has been proposed in literature and recently commercialized. In the field, power converters operates under harsh loading and environmental conditions. The resulting stresses imposed on converter components cause their gradual degradation. In cascaded H-bridge converters, typically power cell components such as power modules, DC-bus capacitors, and control PCBs are v highly stressed. Under these stresses power cell components degrade and require replacement in the field, otherwise unexpected failures may occur. The thesis aim is to address power cell components reliability through proposing novel regenerative cascaded H-bridge converter control schemes to reduce components stresses and failure probability without increasing size, cost, or complexity. First, a novel PWM active front end control scheme has been proposed to reduce the inherent ripple current stresses on the DC-bus capacitors. Second, the thesis proposes a novel grid or near grid switching frequency front end control scheme to reduce stresses on power modules and the power cell cooling requirements. Third, novel cascaded H-bridge front end control schemes are proposed to reduce the sensor count, thereby decreasing failure rate and cutting down cost. The proposed work has been thoroughly validated through detailed 9- cell regenerative cascaded H-bridge system simulation and experimentation. / Thesis / Doctor of Philosophy (PhD)

Nowadays, 3D rendering has been widely applied in video games. Every year companies strive to come up with new solutions and implementations that potentially will increase the complexity of an algorithm, combined with trying to improve the realism of the graphics. An algorithm called Cascaded Shadow Maps will be compared and experimented upon with a regular Shadow Maps algorithm. To further provide information regarding the subject at hand. Objectives. The aim of this experiment is to implement Shadow Maps and Cascaded Shadow Maps in Unity and compare said algorithms to each other. Furthermore, come to a conclusion of which algorithms perform better. Data that will be researched is the Frame rate, Memory consumption, RAM, and Total memory used with the help of Unity's built-in tools. Methods. Shadow Maps and Cascaded Shadow Maps were implemented in Unity Engine by the following literature. Additionally, with help of built-in tools from unity, the Unity Profiler Module. It was possible to take measures to compare each technique of said data. The data were collected five times and then calculated into an average number. Resulting in a collection of data structured and displayed with graphs. Lastly, analyses were performed based on collected data. Results. The data measured and compared showed that Shadow Maps were superior to Cascaded Shadow Maps regarding frame rate, memory consumption, and total memory used. However, Cascaded Shadow Maps could be considered as a algorithm with better complexity to quality ratio than Shadow Maps.  Conclusions. It is Concluded that the Cascaded Shadow Maps utilizes more resources, having less frame rate, higher memory consumption and total memory used. However, Cascaded Shadow Maps were proven in some cases to have better complexity to quality ratio. Additionally, Cascaded Shadow Maps solves the problem Shadow Maps creates, Aliasing. Leads to well-rounded and improved shadows for realism with Cascaded Shadow Maps and in some cases at a small cost.

A new architecture for a frequency synthesizer with adjustable output frequency range and channel spacing is introduced. It is intended for the generation of closely spaced frequency channels in the GHz range while producing minimal spurious phase noise components. The architecture employs two independent phase-locked loops that are driven in cascade by a single reference oscillator. The approach provides fine resolution and wide bandwidth as well as low phase noise and should find application in many contemporary communication systems. The synthesizer can be operated in either of two different modes: nonfractional and mini-denominator fractional modes. The architecture produces no fractional spurs in the first mode and relatively small phase spurs when operated in the second mode. For example, in an application to a P-GSM 900 system, it is capable of tuning from 890 – 915 MHz with a channel spacing of 200 kHz and shows worst case phase spurs of -100 dBc at an offset frequency of 833 kHz. Because of the low magnitude and location of the worst case spurs, the phase-locked loop filters can be designed with a wide bandwidth which in turn results in a fast settling time. A linear frequency-switching settling time (to 0.01% of frequency increments) of 128 μs is typical in the P-GSM 900 application.

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Background. The game-industry is rapidly demanding more and more comput-ing power in its strive for more realistic renditions of environments, simulations andgraphics. To accelerate the improvements made to the realism of real time graph-ics further, optimizations like Clustered and Cascaded Clustered Shading come intoplay. The purpose of these techniques is to reduce the time it takes to render aframe by dividing the view frustum into smaller segments called clusters that canthen be used for light calculations. Cascaded Clustered Shading is a slightly morecustomizable method which aims to improve on Clustered Shading by allowing morecontrol over how the view frustum is divided into clusters. Objectives. The goal of our thesis is to explore the effectiveness of Cascaded Clus-tered Shading compared to Clustered Shading in a scene with 64, 256, 1024 and 4096lights respectively. It is also to find the trend of what type of subdivision pattern thatperforms best in what situation. Thus proving or disproving the theory that moreuniform cluster sizes are beneficial in reducing the complexity of light calculations incomparison to the increasing cluster sizes present in Clustered Shading. Methods. To answer these questions we implemented the techniques in a test scenewhere we could easily compare the performance of the different subdivision patternsand techniques with 64, 256, 1024 and 4096 lights respectively. Three different pat-terns were tested, one with an increasing number of subdivisions per layer P1 (anincrease in the number of clusters per layer). One with a static number of subdi-visions per layer P2, representing the performance of Clustered Shading. One witha decreasing number of subdivisions per layer P3. Additional performance metricsto be recorded were added, measuring the time it took for the different parts of thetechnique so that not just the general performance could be compared. Thus themethod used was a quantitative research method of implementation and experimen-tation. Results. The results supports the theory that more uniform cluster sizes tend tobe beneficial when rendering a scene with many lights showing a clear trend to favora pattern creating more uniform clusters P1. However the results also show a con-tradicting overall performance increase (comparing FPS) using the reversed patternwith sharply increasing cluster sizes based on the distance from the camera P3. Theoverall performance of pattern P1 and P3 was better than P2. Conclusions. The conclusions drawn from the results are that Cascaded ClusteredShading perform better than Clustered Shading in most cases depending on the pat-tern, and that more uniform cluster sizes are beneficial when rendering many lightsin most cases.

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A major objective in speech coding is to represent speech with as few bits as possible. Usual transmission parameters include auto regressive parameters, pitch parameters, excitation signals and excitation gains. The pitch predictor makes these coders sensitive to channel errors. Aiming for robustness to channel errors, we do not use pitch prediction and compensate for its lack with a better representation of the excitation signal. We propose a new speech coding approach, Vector Sum Excited Cascaded Linear Prediction (VSECLP), based on code excited linear prediction. We implement forward linear prediction using five cascaded second order sections - parameterized in terms of line spectral frequency - in place of the conventional tenth order filter. The line spectral frequency parameters estimated by the Direct Line Spectral Frequency (DLSF) adaptation algorithm are closer to the true values than those estimated by the Cascaded Recursive Least Squares - Subsection algorithm. A simplified version of DLSF is proposed to further reduce computational complexity. Split vector quantization is used to quantize the line spectral frequency parameters and vector sum codebooks to quantize the excitation signals. The effect on reconstructed speech quality and transmission rate, of an increased number of bits and differently split combinations, is analyzed by testing VSECLP on the TIMIT database. The quantization of the excitation vectors using the discrete cosine transform resulted in segmental signal to noise ratio of 4 dB at 20.95 kbps, whereas the same quality was obtained at 9.6 kbps using vector sum codebooks. / Master of Science