A long-standing difficulty with rendering huge distances is depth-fighting; a visual artefact produced when two or more fragments overlap either due to coplanar geometry or insufficient depth precision. This thesis presents two novel methods, Cascaded Deferred Rendering (CDR) and Logarithmic Cascaded Deferred Rendering (LogCDR), as a solution to solve depth-fighting that is due to insufficient depth precision. This thesis also evaluates an existing method, logarithmic depth buffer, comparing it against the standard depth buffer in OpenGL, CDR and LogCDR. The most prominent solution found was logarithmic depth buffer because of performance, no overhead from frustum division and extensive culling, ease of implementation and conveniences such as easier implementation of transparency. / Ett långvarigt problem med att rendera stora scener är depth-fighting; en visuell artefakt som uppstår när två eller flera fragments överlappar, antingen för att det är ligger direkt på varandra eller för att det inte finns nog med precision i djupbuffern. Detta examensarbete presenterar två nya metoder, Cascaded Deferred Rendering (CDR) och Logarithmic Cascaded Deferred Rendering (LogCDR) som en lösning på depth-fighting som framträder när de inte finns nog med precision. Detta examensarbete utvärderar också en redan existerande metod, logaritmisk djupbuffer, och jämför den med standard djupbuffern i OpenGL, CDR samt LogCDR. Den mest lovande metoden funnen var logaritmisk djupbuffer för dess hastighet, lätthet att implementera och enklare att lägga till stöd för transparans till.

Den klassiska approachen till navigering innefattar att agenten håller en intern representativ modell av omgivningen. Denna approach har emellertid många nackdelar, speciellt för dynamiska miljöer. En modernare approach är att förlita sig på den faktiska omgivningen istället för en modell av denna. Detta arbete presenterar en undersökning av navigeringsproblemet och hur väl det löses av agenter vars kontrollmekanismer utgörs artificiella neurala nätverk. Tillförlitligheten hos de två neurala arkitekturerna Extended sequential cascaded network och Self-organized recurrent network bestäms genom experiment. Det visas i experimenten att Extended sequential cascaded network är den mest tillförlitliga arkitekturen av de två när navigeringsproblemet skall angripas. Det visas även att Extended sequential cascaded network tränar fram ett helt reaktivt beteende i samtliga experiment. Slutsatsen som kan dras av detta är att svåra problem inte alltid kräver avancerade arkitekturer för att lösastillfredsställande.

Den situerade ansatsen inom artificiell intelligens har i tidigare experiment visat på stora möjligheter vid utvecklingen av enkla beteenden. Ansatsens framgångar är dock inte lika tydliga när det kommer till utvecklingen av mer komplexa beteenden som i högre grad påminner om de experiment som gjorts inom traditionell artificiell intelligens. I studien utvecklas en agent med ett ”Extended Sequential Cascaded Network” som kontrollarkitektur för att lösa en uppgift som kräver ett ”räkneliknande beteende”. Utvecklingen av nätverket grundas på en situerad syn på kognition, däribland att designern i så liten grad som möjligt skall styra utvecklingen. Experimentets resultat visar på en agent som inte ens löser den enklaste versionen av uppgiften. I diskussionen härleds misslyckandet till svårigheterna med en designeroberoende utveckling.

Morphological segmentation while reading is essential for new vocabulary learning. The study's aim was to investigate semantic-level morphological segmentation using event-related brain potentials (ERPs) in typical young adult readers. Past research has suggested that, because semantically opaque words prime their stems (e.g., corner/corn) similarly to transparent words (e.g., farmer/farm), readers recognize complex words from their constituent morphemes without regard to semantic information. However, this priming effect may be due to orthographic and phonological overlap between prime and target words. The research presented here addressed this possibility by creating five conditions in which orthographic, phonological, and semantic relationships between prime and target words were manipulated: Condition 1,wherein prime and target shared no relationship (e.g., inn/brother), served as Control. In Condition 2, prime and target were the same (e.g., brother/brother). In Condition 3, prime was the stem of target (e.g., broth/brother). Condition 4, our critical experimental condition, used primes semantically related to the stem of the target word (e.g., soup/brother). Finally, in Condition 5, prime was semantically related to the whole target word (e.g., sibling/brother). Semantically priming the stem (Condition 4) did not modulate the amplitude of the standard N400 ERP component (as did Conditions 2, 3, and 5), but did affect an early N400-like ERP component peaking in amplitude at ~262 ms after target. Other ERPs were observed that responded uniquely to shared orthography (Conditions 2, 3). Results set the stage for investigating morphological processing in adult reading impairments to evaluate whether, and to what extent, these readers semantically process morphological stems during text comprehension.

abstract: Thermal Energy Storage (TES) is of great significance for many engineering applications as it allows surplus thermal energy to be stored and reused later, bridging the gap between requirement and energy use. Phase change materials (PCMs) are latent heat-based TES which have the ability to store and release heat through phase transition processes over a relatively narrow temperature range. PCMs have a wide range of operating temperatures and therefore can be used in various applications such as stand-alone heat storage in a renewable energy system, thermal storage in buildings, water heating systems, etc. In this dissertation, various PCMs are incorporated and investigated numerically and experimentally with different applications namely a thermochemical metal hydride (MH) storage system and thermal storage in buildings. In the second chapter, a new design consisting of an MH reactor encircled by a cylindrical sandwich bed packed with PCM is proposed. The role of the PCM is to store the heat released by the MH reactor during the hydrogenation process and reuse it later in the subsequent dehydrogenation process. In such a system, the exothermic and endothermic processes of the MH reactor can be utilized effectively by enhancing the thermal exchange between the MH reactor and the PCM bed. Similarly, in the third chapter, a novel design that integrates the MH reactor with cascaded PCM beds is proposed. In this design, two different types of PCMs with different melting temperatures and enthalpies are arranged in series to improve the heat transfer rate and consequently shorten the time duration of the hydrogenation and dehydrogenation processes. The performance of the new designs (in chapters 2 and 3) is investigated numerically and compared with the conventional designs in the literature. The results indicate that the new designs can significantly enhance the time duration of MH reaction (up to 87%). In the fourth chapter, organic coconut oil PCM (co-oil PCM) is explored experimentally and numerically for the first time as a thermal management tool in building applications. The results show that co-oil PCM can be a promising solution to improve the indoor thermal environment in semi-arid regions. / Dissertation/Thesis / Doctoral Dissertation Mechanical Engineering 2020

Thesis (MScEng)--Stellenbosch University, 2011. / ENGLISH ABSTRACT: The Solid-State Transformer (SST) is presented as an alternative to the traditional Line-Frequency Transformer (LFT) used for voltage-level transformation in distribution grids. The LFT technology is highly matured which results in low costs and high efficiency. The SST however, introduces several advantages compared to the LFT, some of which are input unity power-factor, near perfect output-voltage regulation, frequency variation as well as harmonic filtering. The SST consists of three power-electronic converter stages: The input stage, the isolation stage and the output stage. The input and isolation stages are implemented with a multilevelconverter topology incorporating a converter-stack for each phase. Each stack consists of N converter building blocks, called cells. In this thesis the design and implementation of the main controller is presented. The main controller, together with N cell controllers, is responsible for the control of the cells within the respective stack. Three main controllers are thus implemented within the SST. Each cell consists of an Active Rectifier (AR) and a DC-DC Converter (DC-DC). The SST control design thus starts with the AR control which is subsequently expanded to Cascaded Active-Rectifier (CAR) control. Design is completed with the addition of the DC-DC control. Time domain simulations of the AR- and CAR-control are presented and discussed. Test measurements, verifying functionality of each control design-phase, are presented and discussed. / AFRIKAANSE OPSOMMING: Die Drywingselektroniese Transformator (DET) word voorgestel as ’n alternatief vir die Lyn Frekwensie Transformator (LFT) wat gebruik word vir spannings-vlak tranformasie op distribusie vlak. The LFT tegnologie is ver gevorderd wat ly tot hoë effektiwiteit en lae kostes. The DET bied wel voordele soos intree eenheids arbeid faktor, na aan perfecte uittree-spannings regulasie, frequensie variasie sovel as harmoniese filrteering. Die DET bestaan uit drie drywingselektroniese omsetter stadiums: Die intree-stadium, die isolasie-stadium en die uittree-stadium. The intree- en isolasie-stadiums word geïmplimenteer met ’n multivlak-omsetter topologie wat bestaan uit ’n omsetter-stapel vir elke fase. Elke stapel bestaan uit N omsetter boustene wat selle genoem word. In hierdie tesis word the ontwerp en implementasie van die hoofbeheerder voorgestel. Die hoofbeheerder, tesame met N selbeheerders, is verantwoordelik vir die beheer van elke sel in die spesifieke stapel. In die DET word daar dus drie hoofbeheerders gebruik. Elke sel bestaan uit ’n Aktiewe Gelykrigter (AG) en ’n GS-GS omsetter (GS-GS). Die DET beheerontwerp begin dus met die (AG) beheer wat daarna uitgebrei word na Kaskade Aktiewe Gelykrigter (KAG) beheer. Die beheer ontwerp word voltooi deur die byvoeging van die GSGS beheer. Tyd-gebied simulasies van die AG- en KAG-beheer word voorgelê en bespreek. Toetsmetings wat die funksionaliteit van elke beheer ontwepsfase verifeer, word voorgelê.

Dans cette thèse, les recherches ont été menées à des niveaux d'abstraction différents pour optimiser le fonctionnement du modulateur ΣΔ passe-haut (PH). Une approche « top-down » est adoptée pour atteindre cet objectif. Au niveau de l'architecture du récepteur RF, le nouvellement créé récepteur Fs/2 est sélectionné pour sa grande compatibilité avec modulateur ΣΔ PH comparé aux architectures de réception: zéro-IF et faible-IF. Après avoir défini la topologie du récepteur, l'architecture du modulateur ΣΔ est adressée. Nous proposons une nouvelle architecture du deuxième ordre dont la fonction de transfert du signal est unitaire. Elle est plus avantageuse que d'autres topologies en termes de complexité et de performance. Puisque le modulateur de second ordre est incapable de fournir les performances requises, les structures en cascade ou MASH pour l'opération PH sont explorées. La topologie GMSCL (Generalized Multi-Stage Closed Loop) est choisie et une technique récemment proposée est appliquée pour linéariser le CNA de retour. En plus, cette technique augmente la plage dynamique du convertisseur. Ensuite, après une analyse comparative approfondie, le meilleur filtre HP est choisie pour ce modulateur. Il a les avantages d'avoir une basse consommation, une superficie réduite et un bruit moins important. Enfin, l'architecture GMSCL PH proposée est validée en CMOS 65nm. Les applications visées sont l'UMTS avec 3.84MHz bande de conversion à 80 dB de la plage dynamique et WiMAX avec 25MHz de bande passante à 52dB de dynamique.

Cette thèse est dédiée aux convertisseurs multiniveaux et aborde les problématiques liées à la compensation des perturbations générées sur un réseau électrique, telles que celles produites par les fours à arc. Elle est composée de quatre chapitres couvrant les thématiques de la modélisation des réseaux électriques, des convertisseurs de tension, du contrôle commande et des stratégies de compensation, accompagnés de simulations et de résultats expérimentaux obtenus sur des équipements industriels de forte puissance. Les applications réseaux étant diverses et variées, les convertisseurs multiniveaux sont ici étudiés dans le but d’être raccordés directement sur des réseaux de distribution. Pour cela, un état de l’art des différentes topologies de convertisseurs de tension (classiques et multiniveaux) est présenté et les topologies dites modulaires, sont retenues pour une étude plus poussée. Ces convertisseurs utilisent des modules de puissance à base de ponts en H, de ½ ponts en H ou de ponts en H 3-niveaux connectés en cascade. Ils permettent ainsi de créer différents types de configurations ou couplages appelés dans ce mémoire : étoile, triangle et étoiles symétriques. Les différents modules et les stratégies pour les commander sont étudiés autour d’un composant de puissance (de type IGBT 2.5kV/1.5kA). A travers les domaines électrique et thermique, une méthode est proposée afin d’estimer les pertes, les températures de jonction et déterminer ainsi les limites d’utilisation d’un tel composant de puissance. Le dimensionnement et la fiabilité de ces convertisseurs est également abordé pour chacune des configurations envisagées, afin de dégager les avantages et inconvénients pour une application réseau. D’une façon générale, la stratégie de contrôle des convertisseurs multiniveaux est ardue, principalement lié au fait que de multiples sources de tensions continues doivent être contrôlées. Dans cette optique, des stratégies de contrôle sont proposées et validées en simulation selon les types de modules et de configurations utilisés pour la compensation des perturbations d’un four à arc. Enfin, la dernière partie de ces travaux est consacrée aux résultats expérimentaux sur la base d’un compensateur industriel dénommé DSVC (Dynamic Static Var Compensator), pour la compensation des fours à arc. Les différents résultats obtenus sur plusieurs sites industriels ont ainsi permis la validation des travaux exposés dans ce mémoire / This thesis is dedicated to the multilevel converters and addresses issues related to compensation for disturbance generated on an electrical network such as those produced by arc furnaces. It is composed of four chapters covering the themes of modeling of electrical networks, voltage converters, control and compensation strategies, with simulations and experimental results obtained on high power industrial equipment. There are many networks applications and multilevel converters are here considered to be directly connected to distribution networks. Therefore, a state of the art of different voltage converters, classics and multilevel topologies, is presented and the topologies called modular are retained for further studies. These converters use modular power cells made of H bridges, ½ bridges or 3-level H bridges connected in cascade. They allow to create different types of configurations or couplings called in this memory: star, delta and double stars. The different modules and the strategies to control them are investigated around the same switching power component (IGBT 2.5kV/1.5kA). Through electrical and thermal fields, a method is proposed to estimate their losses, junction temperatures in order to determine the limits of use of such a component of power. Sizing and reliability of these converters is also discussed for each considerer configurations in order to identify the advantages and disadvantages for a network application. Generally, the multilevel converters control strategy is difficult because of the multiple sources of DC voltages to control. In this context, control strategies are proposed and validated in simulation according to the types of modules and configuration used to compensation for disturbance of an arc furnace. Finally, the last part of this thesis is devoted to the experimental results based on an industrial compensator DSVC (Dynamic Static Var Compensator) for arc furnace compensation. The different results obtained at several industrial sites have thus allowed the validation of the various works exposed in this thesis

Microwave limiting amplifiers are the key components of Instantaneous Frequency Measurement (IFM) systems. Limiting amplifiers provide constant output power level in a wide input dynamic range and over a broad frequency band. Moreover, limiting amplifiers are high gain devices that are used to bring very low input power levels to a constant output power level. Besides, limiting amplifiers are required to provide minimum small signal gain ripple in order not to reduce the sensitivity of the IFM system over the operating frequency band. In this thesis work, a high gain, medium power, 2-18 GHz limiting amplifier module is designed, simulated, fabricated and measured. First, a 3-stage cascaded amplifier with 27 dB small signal gain is designed and fabricated. The 3-stage amplifier is composed of a novel cascaded combination of negative feedback and distributed amplifiers that provides the minimum small signal gain ripple and satisfactory input and output return losses inside 2-18 GHz frequency band. Then, the designed two 3-stage amplifiers and one 4-stage amplifier are cascaded to constitute a limiting amplifier module with minimum 80 dB small signal gain. The designed 10-stage limiting amplifier module also includes an analog voltage controllable attenuator to be used for compensating the gain variations resulting from temperature changes. The fabricated 10-stage limiting amplifier module provides 20 +/- 1.2 dBm output power level and excellent small signal gain flatness, +/- 2.2 dB, over 2-18 GHz frequency range.

The Internet of Things (IoTs) has triggered rapid advances in sensors, surveillance devices, wearables and body area networks with advanced Human-Computer Interfaces (HCI). Neural Networks optimized algorithmically for high accuracy and high representation power are very deep and require tremendous storage and processing capabilities leading to higher area and power costs. For developing smart front-ends for ‘always on’ sensor nodes we need to optimize for power and area. This requires considering trade-offs with respect to various entities such as resource utilization, processing time, area, power, accuracy etc. Our experimental results show that there is presence of a network configuration with minimum energy given the input constraints of an application in consideration. This presents the need for a hardware-software co-design approach. We present a highly parameterized hardware design on an FPGA allowing re-configurability and the ability to evaluate different design choices in a short amount of time. We also describe the capability of extending our design to offer run time configurability. This allows the design to be altered for different applications based on need and also allows the design to be used as a cascaded classifier beneficial for continuous sensing for low power applications. This thesis aims to evaluate the use of Restricted Boltzmann Machines for building such re-configurable low power front ends. We develop the hardware architecture for such a system and provide experimental results obtained for the case study of Posture detection for body worn cameras used for law enforcement.