With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this thesis, we present a radiation hardened PLL design. Each of the components of this design-the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the charge pump/loop filter-are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our design uses two VCOs (with cross-coupled inverters) and charge pumps, so that a strike on any one is compensated by the other. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our SPICE-based results demonstrate that after exhaustively striking all circuit nodes, the worst case jitter of our hardened PLL is just 37.4 percent. In the worst case, our PLL returns to the locked state in 2 cycles of the VCO clock, after a radiation strike. These numbers are significant improvements over those of the best previously reported approaches.

The objective of this thesis is to introduce an alternative temperature sensor in CMOS technology with small area, low power consumption, and high resolution that can be easily interfaced. A novel temperature sensor utilizing the interface–trap charge pumping phenomenon and the temperature sensitivity of generation current is proposed. This thesis presents the design and characterization of the proposed temperature sensor fabricated in 0.18µm CMOS technology. The prototype sensor is characterized for the temperature range of 27oC–120oC. It has frequency output and exhibits linear transfer characteristics, high sensitivity, and high resolution. This temperature sensor is proposed for microprocessor thermal management applications.

This thesis presents a low power consumption, low phase noise, and fast locking CMOS fractional-N frequency synthesizer with optimalied voltage-controlled oscillator. The frequency synthesizer is designed in a TSMC 0.18£gm CMOS 1P6M technology process. It can be used for IEEE 802.16e mobile Wimax¡¦s devices and outputing frequency is ranged from 2.3GHz to 2.45GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump (CP), a low-pass loop filter (LPF), a voltage-controlled oscillator (VCO), a multi-modulus divider, and a delta-sigma modulator (DSM). In system design, two voltage-controlled oscillators we presented to achieve low power consumption, low phase noise, and stable output swing. Delta-sigma modulator (DSM) is adopted to produce high frequency resolution, switching over frequency fast and very low phase noise. This thesis proposes a switch circuit which can reduce the lock of time of synthesizer. In the mean time it also reduces the emergence of lose lock.

In the present thesis, I have proposed methodology of two stages Dickson charge pump, which is capable of harvesting energy at 2.45 GHz RF signal to power any low powered device. Presented design uses a simple and inexpensive circuit consisting of four microstrip patch antennas, some zero-bias Schottky diodes, Wilkinson power divider and a few passive components. Circuit was fabricated on a 60 mils RO4350B substrate (=3.66), with 1.4 mils copper conductor. Demonstration showed the charge pump provides a good performance, as it drives the low powered devices with as low as 10dBm input power at 1m away from the energy source. Thesis paper will present design techniques illustrated with data obtained on prototype circuits. The objective is to wirelessly gather energy from one RF source and convert it into usable DC power that is further applied to a set of low power electronic devices. Radio Frequency Identification (RFID) tag system could also be improved using this method. RF-to-DC conversion is accomplished by designing and characterizing an element commonly known as a Rectenna, which consists of an antenna and an associated rectification circuitry. The rectenna is fully characterized in this dissertation and is used for charging low powered devices.

The objective of this research is to develop an embedded, wireless, energy-harvesting prototype (E-WEHP) that can power on and sustain embedded sensing functions using the power present in ambient wireless signals in urban areas. This research is part of a bigger effort towards greening RF circuits and applications in order to reduce their pollution foot-print. Pollution due to modern electronics is primarily caused by non-biodegradable packaging waste and batteries that form a big part of most electronics. Electronic waste can especially be a nuisance in RFID and wireless sensors that are mass-produced and widely-used in consumer items, buildings, industries, agriculture and transportation. The first part of this research effort addresses the issue of minimizing electronic packaging waste by characterizing and using biodegradable substrates such as Paper and Perfluoropolymer (PFA) as a dielectric material in RF circuits. Towards this goal, the first of its kind active wireless sensor modules made of biodegradable paper substrate using a clean and novel inkjet-printing technology is developed and successfully operated in the 900 MHz free ISM band. The second and third part of this research effort addresses the issue of battery waste by investigating the use of ambient solar and wireless radiation for powering RF and embedded electronics for wireless localization and sensing applications without the use of batteries. The second part of this work presents a unique solar-powered tag called SOLTAG that combines solar cells along with an RFID-type powering mechanism to implement a very low-cost, battery-less, semi-passive wireless-tag but with a much longer range than passive EPC-Gen2 RFID tags. A GPS-like, low-cost, vehicle-tracking system based on a received-signal-strength-indication method using SOLTAGs in vehicles and a wireless network of Mica-motes is successfully developed and tested with accuracy down to 1.62 meters The third and main part of this research work presents a novel embedded-wireless-energy-harvesting-prototype (E-WEHP) that can successfully power-on and sustain sensing and M2M peripherals in a 16-bit microcontroller using the power present in ambient, wireless, Digital-TV signals without the use of batteries. This work involves an in-depth characterization of OFDM signals used in Digital-TV broadcasts in Tokyo and Atlanta along with the design and development of the E-WEHP hardware and firmware that exploits the multi-carrier nature of such TV signals for powering itself at a range of over 6 km from the TV broadcast sources. This work opens up the possibility of pervasively powering sensor motes for applications such as environmental sensing, smart homes, structural health monitoring, security and internet of things without the environmental and logistical cost of periodic battery replacement and disposal.

abstract: Implantable medical device technology is commonly used by doctors for disease management, aiding to improve patient quality of life. However, it is possible for these devices to be exposed to ionizing radiation during various medical therapeutic and diagnostic activities while implanted. This commands that these devices remain fully operational during, and long after, radiation exposure. Many implantable medical devices employ standard commercial complementary metal-oxide-semiconductor (CMOS) processes for integrated circuit (IC) development, which have been shown to degrade with radiation exposure. This necessitates that device manufacturers study the effects of ionizing radiation on their products, and work to mitigate those effects to maintain a high standard of reliability. Mitigation can be completed through targeted radiation hardening by design (RHBD) techniques as not to infringe on the device operational specifications. This thesis details a complete radiation analysis methodology that can be implemented to examine the effects of ionizing radiation on an IC as part of RHBD efforts. The methodology is put into practice to determine the failure mechanism in a charge pump circuit, common in many of today's implantable pacemaker designs, as a case study. Charge pump irradiation data shows a reduction of circuit output voltage with applied dose. Through testing of individual test devices, the response is identified as parasitic inter-device leakage caused by trapped oxide charge buildup in the isolation oxides. A library of compact models is generated to represent isolation oxide parasitics based on test structure data along with 2-Dimensional structure simulation results. The original charge pump schematic is then back-annotated with transistors representative of the parasitic. Inclusion of the parasitic devices in schematic allows for simulation of the entire circuit, accounting for possible parasitic devices activated by radiation exposure. By selecting a compact model for the parasitics generated at a specific dose, the compete circuit response is then simulated at the defined dose. The reduction of circuit output voltage with dose is then re-created in a radiation-enabled simulation validating the analysis methodology. / Dissertation/Thesis / M.S. Electrical Engineering 2010

abstract: A single solar cell provides close to 0.5 V output at its maximum power point, which is very low for any electronic circuit to operate. To get rid of this problem, traditionally multiple solar cells are connected in series to get higher voltage. The disadvantage of this approach is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT) at single solar cell level is the most efficient way to extract power from solar cell. Power Management IC (MPIC) used to extract power from single solar cell, needs to start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input. The auxiliary supply powers up a MPPT converter followed by a regulated converter. At the start up both the converters operate at 100 kHz clock with 80% duty cycle and system output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up circuit is turned off and the supply voltage for both the converters is derived from the system output itself. In steady-state condition the system output is regulated to 3.0 V. A fully integrated analog MPPT technique is proposed to extract maximum power from the solar cell. This technique does not require Analog to Digital Converter (ADC) and Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed MPPT techniques includes a switch capacitor based power sensor which senses current of boost converter without using any sense resistor. A complete system is designed which starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2015

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第22658号 / 工博第4742号 / 新制||工||1741(附属図書館) / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 篠原 真毅, 教授 守倉 正博, 教授 小嶋 浩嗣 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

<div>With the growing popularity and use of devices under the great umbrella that is the Internet of Things (IoT), the need for devices that are smaller, faster, cheaper and require less power is at an all time high with no intentions of slowing down. This is why many current research efforts are very focused on energy harvesting. Energy harvesting is the process of storing energy from external and ambient sources and delivering a small amount of power to low power IoT devices such as wireless sensors or wearable electronics. A charge pumps is a circuit used to convert a power supply to a higher or lower voltage depending on the specific application. Charge pumps are generally seen in memory design as a verity of power supplies are required for the newer memory technologies. Charge pumps can be also be designed for low voltage operation and can convert a smaller energy harvesting voltage level output to one that may be needed for the IoT device to operate. In this work, an integrated FinFET (Field Effect Transistor) charge pump for low power energy harvesting applications is proposed.</div><div><br></div><div>The design and analysis of this system was conducted using Cadence Virtuoso Schematic L-Editing, Analog Design Environment and Spectre Circuit Simulator tools using the 7nm FinFETs from the ASAP7 7nm PDK. The research conducted here takes advantage of some inherent characteristics that are present in FinFET technologies, including low body effects, and faster switching speeds, lower threshold voltage and lower power consumption. The lower threshold voltage of the FinFET is key to get great performance at lower supply voltages.</div><div><br></div><div>The charge pump in this work is designed to pump a 150mV power supply, generated from an energy harvester, to a regulated 650mV, while supplying 1uA of load current, with a 20mV voltage ripple in steady state (SS) operation. At these conditions, the systems power consumption is 4.85uW and is 31.76% efficient. Under no loading conditions, the charge pump reaches SS operation in 50us, giving it the fastest rise time of the compared state of the art efforts mentioned in this work. The minimum power supply voltage for the system to function is 93mV where it gives a regulated output voltage of 425mV.</div><div><br></div><div>FinFET technology continues to be a very popular design choice and even though it has been in production since Intel's Ivy-Bridge processor in 2012, it seems that very few efforts have been made to use the advantages of FinFETs for charge pump design. This work shows though simulation that FinFET charge pumps can match the performance of charge pumps implemented in other technologies and should be considered for low power designs such as energy harvesting.</div>

Phase Synthesis is a fundamental operation in Smart Antennas and other Phased Array systems based on beamforming. There are increasing commercial applications for Integrated Phased Arrays due to their low cost, size and power and also because the RF and digital signal processing can be performed on the same chip. These low cost beamforming applications have augmented interest in Coupled Phase Locked Loop (CPLL) systems for Phase Synthesis. Previous work on the implementation of Phase Synthesis systems using Coupled PLLs for low cost beamforming had the constraint of a limited phase range of ±90°. The idea behind the thesis is that this phase synthesis range can be increased to ±180° through the use of PLLs employing Phase Frequency Detectors(PFDs), which is a significant improvement over conventional coupled-PLL systems. This work presents the detailed design and measurement results for a phase synthesizer using Coupled PLLs for achieving phase shift in the range of ±180°. Several Coupled PLL architectures are investigated and their advantages and limitations are evaluated in terms of frequency controllability, phase difference synthesis control and phase noise of the systems. A two-PLL system implementation using off the shelf components is presented, which generates a steady-state phase difference in the range ±180° using an adjustable DC control current. This is the proof of concept for doing an IC design for a Coupled Phase Locked Loop system. Commercial applications in the Wireless Medical Telemetry Service (WMTS) band motivate the design of a CPLL system in the 608-614 MHz band. The design methodology is presented which shows the flowchart of the IC design process from the system design specifications to the transistor level design. MATLAB simulations are presented to model the system performance quickly. VerilogA modeling of the CPLL system is performed followed by the IC design of the system and each block is simulated under different process and temperature corners. The transistor level design is then evaluated for its performance in terms of phase difference synthesis and phase noise and compared with the initial MATLAB analysis and improved iteratively. The CPLL system is implemented in IBM 130nm CMOS process and consumes 40mW of power from a 1.2V supply with a phase noise performance of -88 dBc/Hz for 177° phase generation.