Nesse trabalho é apresentada uma arquitetura que habilita a geração de MPSoCs (Multiprocessors Systems-on-Chip) heterogêneos escaláveis, baseados em barramento, suportando ainda o uso de diferentes organizações de memória. A comunicação entre as tarefas é especificada por meio de uma estrutura de memória compartilhada, que evita colisões e promove ganhos energéticos através do disparo dinâmico de clock gating. Também é introduzida a técnica DCF (Dynamic Core Freezing), que incrementa a eficiência energética do MPSoC tirando proveito dos ciclos ociosos dos processadores durante os acessos à memória. Mais, a combinação das organizações de memória propostas habilita a exploração de migração de tarefas na arquitetura proposta, por meio da troca de contexto das tarefas na memória compartilhada. Além disso, é mostrado o simulador de alto-nível, baseado na arquitetura proposta, criado com o propósito de extrair os ganhos energéticos propiciados com o uso do clock gating e da técnica DCF. O simulador aceita como entrada arquivos de trace de execução de aplicações Java, com os quais ele gera um novo arquivo contendo o mapeamento das instruções encontradas nos arquivos de trace para diferentes classes de instrução. Dessa forma, podem ser modeladas diferentes arquiteturas de processadores, usando o arquivo com o mapeamento para simular o MPSoC. Mais, o simulador habilita ainda a exploração das diferentes organizações de memória da arquitetura proposta, de maneira que se pode estimar o seu impacto no número de instruções executadas, contenções no barramento, e consumo energético. Experimentos baseados em uma aplicação sintética, executando em um MPSoC composto por diferentes versões de um processador Java mostram um grande aumento na eficiência energética com um custo mínimo em área. Além disso, também são apresentados experimentos baseados em aplicações do benchmark SPECjvm98, que mostram o impacto causado na eficiência energética quando o tipo de aplicação é alterado. Mais, os experimentos mostram drásticos ganhos energéticos obtidos com a aplicação da técnica DCF sobre as memórias do MPSoC. / In this work we present an architecture that enables the generation of bus-based, scalable heterogeneous Multiprocessor Systems-on-Chip (MPSoCs), supporting different memory organizations. Intertask communication is specified by means of a shared memory structure that assures collision avoidance and promotes energy savings through a dynamic clock gating triggering. We also introduce a Dynamic Core Freezing (DCF) technique, which boosts energy savings taking advantage of processor idle cycles during memory accesses. Moreover, the combination of the memory organizations enables the architecture to exploit easy task migration by means of the task context saving in the shared data memory. Moreover, we show the high-level simulator, based on the proposed architecture, created in order to extract the energy savings enabled with the clock gating and the DCF techniques. The simulator accepts as input execution trace files of Java applications, from which it generates a new file that contains the mapping of the instructions found in the trace file for different instruction classes. This way, we can model different processor architectures, using the mapping file to simulate the MPSoC. Also, the simulator enables us to experiment with different memory organizations to estimate their impact on the executed instructions, bus contention, and energy consumption. As case study we have modeled different versions of a Java processor in order to experiment with different execution patterns over different memory organizations. Experiments based on a synthetic application running on an MPSoC containing different versions of a Java processor show a large improvement in energy efficiency with a minimal area cost. Besides that, we also present experiments based on applications of the SPECjvm98 benchmark, which show the impact on the energy efficiency when we change the application type. Moreover, the experiments show a huge improvement in the energy efficiency when applying the DCF technique to the MPSoC memories.

Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC Intra-Only. Na descrição de hardware são acrescidas as técnicas de paralelismo e pipeline. Na síntese física e lógica, incluem-se as técnicas de inativação do relógio ( clock gating), múltiplas tensões de threshold, diferentes tecnologias e diferentes tensões de alimentação. A síntese é feita nas ferramentas da CadenceTM com exploração arquitetural e apresenta uma menor energia por operação, quando exigido desempenho equivalente (isoperformance ) para SAD, em baixa frequência, alto paralelismo e, principalmente, com um estágio de pipeline. Além disso, tecnologias CMOS mais avançadas diminuem o consumo de potência dinâmica e, em alguns casos, também diminuem a potência estática por gate equivalente, se utilizadas células High-VT e tensão de alimentação a menor possível. Outro fator a ser destacado é o uso do clock gating que no caso das arquiteturas de SAD, em vez de diminuir, aumenta o consumo de potência dinâmica. Neste trabalho foi realizada a síntese do decodificador Intra-Only. O decodificador com clock gating apresenta um menor consumo de potência, mostrando um caso em que esta técnica é benéfica. Além disso, a utilização de uma tecnologia CMOS 65 nm e, consequentemente, tensão de alimentação menor, levou a uma sensível diminuição no consumo de potência em relação a outros trabalhos similares. / This work presents low-power techniques applications to digital blocks in the SAD algorithm and in the Intra-Only H.264/AVC decoder. In the hardware description, we add parallelism and pipeline techniques. In the logical and physical synthesis exploration, includes the clock gating, multiple threshold voltage, different technologies and multiple supply voltage. The synthesis are done in the CadenceTM tools and show a smaller energy per operation in isoperformance for SAD at low frequency, high parallelism and, mainly, with one pipeline stage. In addition to that, more advanced CMOS technologies decrease the dynamic power consumption and, also, decrease the static power for equivalent gates, if using High-VT cells and lowest possible power supply. Another factor is the clock gating use that in the SAD architecture, instead of decreasing, increases the dynamic power consumption. In this work the design of an Intra-Only H.264/AVC Decoder was performed. This design with clock gating presents lower power consumption, showing a case in which this technique is beneficial in terms of dynamic power. Besides that, the 65 nm CMOS technology uses a lower power supply, resulting in lower power consumption in comparison to other related works.

Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC Intra-Only. Na descrição de hardware são acrescidas as técnicas de paralelismo e pipeline. Na síntese física e lógica, incluem-se as técnicas de inativação do relógio ( clock gating), múltiplas tensões de threshold, diferentes tecnologias e diferentes tensões de alimentação. A síntese é feita nas ferramentas da CadenceTM com exploração arquitetural e apresenta uma menor energia por operação, quando exigido desempenho equivalente (isoperformance ) para SAD, em baixa frequência, alto paralelismo e, principalmente, com um estágio de pipeline. Além disso, tecnologias CMOS mais avançadas diminuem o consumo de potência dinâmica e, em alguns casos, também diminuem a potência estática por gate equivalente, se utilizadas células High-VT e tensão de alimentação a menor possível. Outro fator a ser destacado é o uso do clock gating que no caso das arquiteturas de SAD, em vez de diminuir, aumenta o consumo de potência dinâmica. Neste trabalho foi realizada a síntese do decodificador Intra-Only. O decodificador com clock gating apresenta um menor consumo de potência, mostrando um caso em que esta técnica é benéfica. Além disso, a utilização de uma tecnologia CMOS 65 nm e, consequentemente, tensão de alimentação menor, levou a uma sensível diminuição no consumo de potência em relação a outros trabalhos similares. / This work presents low-power techniques applications to digital blocks in the SAD algorithm and in the Intra-Only H.264/AVC decoder. In the hardware description, we add parallelism and pipeline techniques. In the logical and physical synthesis exploration, includes the clock gating, multiple threshold voltage, different technologies and multiple supply voltage. The synthesis are done in the CadenceTM tools and show a smaller energy per operation in isoperformance for SAD at low frequency, high parallelism and, mainly, with one pipeline stage. In addition to that, more advanced CMOS technologies decrease the dynamic power consumption and, also, decrease the static power for equivalent gates, if using High-VT cells and lowest possible power supply. Another factor is the clock gating use that in the SAD architecture, instead of decreasing, increases the dynamic power consumption. In this work the design of an Intra-Only H.264/AVC Decoder was performed. This design with clock gating presents lower power consumption, showing a case in which this technique is beneficial in terms of dynamic power. Besides that, the 65 nm CMOS technology uses a lower power supply, resulting in lower power consumption in comparison to other related works.

Les systèmes intégrés sont aujourd’hui de plus en plus fréquemment confrontés à des contraintes de faible consommation ou d’efficacité énergétique. Ces problématiques se doivent d’être intégrées le plus en amont possible dans le flot de conception afin de réduire les temps de design et d’éviter de nombreuses itérations dans le flot. Dans ce contexte, le projet collaboratif HiCool, partenariat entre les laboratoires LIRMM et TIMA, les sociétés Defacto, Docea et ST Microelectronics, a mis en place une stratégie et un flot de conception pour concevoir des systèmes intégrés faible consommation tout en facilitant la réutilisation de blocks matériels (IPs) existants. L’approche proposée dans cette thèse s’intègre dans cette stratégie en apportant une petite dose d’asynchronisme dans des systèmes complètement synchrones. En effet, la réduction de la consommation est basée sur le constat que l’activation permanente de la totalité du circuit est inutile dans bien des cas. Néanmoins, contrôler l’activité avec des techniques de « clock gating » ou de « power gating » nécessitent usuellement d’effectuer un re-design du système et d’ajouter un organe de commande pour contrôler l’activation des zones effectuant un traitement. Le travail présenté dans ce manuscrit définit une stratégie basée sur des contrôleurs d’horloge et de domaine d’alimentation, asynchrones, distribués et facilement insérables dans un circuit avec un coût de re-design des plus réduit. / Today integrated systems are increasingly faced with the constraints of low consumption or energy efficiency. These issues need to be integrated as far upstream as possible in the design flow to reduce design time and avoid much iteration in the flow. In this context, the collaborative project HiCool, between LIRMM and TIMA laboratories, Defacto, Docea and ST Microelectronics companies, has set up a strategy and design flow to design integrated low power systems while facilitating the reuse of existing hardware blocks (IPs). The approach proposed in this thesis fits into this strategy by bringing a small dose of asynchrony in completely synchronous systems. Indeed, the reduction in consumption is based on the observation that permanent activation of the entire circuit is unnecessary in many cases. However, controlling the activity with techniques of "clock gating" or "power gating" usually need to perform a re-design of the system and to add a control device for controlling activation of areas effecting treatment. The work presented in this manuscript provides a strategy based clock controllers and power domain, asynchronous, distributed and easily insertable into a circuit with a low cost design.

With FinFET based Application Specific Integrated Circuit (ASIC) designs delivering on the promises of scalability, performance, and power, the road ahead is bumpy with technical challenges in building efficient ASICs. Designers can no longer rely on the ‘auto-scaling’ power reduction that follows technology node scaling, in these times when 7nm presents itself as a ‘long-lived’ node. This leads to the need for early power analysis and reduction flows that are incorporated into the ASIC Intellectual Property (IP) design flow. This leads to a focus on power-efficient design in addition to being functionally efficient. Power inefficiency related hotspots are the leading causes of chip re-spins, and a guideline methodology to design blocks in a power-efficient manner leads to a power-efficient design of the Integrated Circuits (ICs). This alleviates the intensity of cooling requirements and the cost. The Common Memory controller is one of the leading consumers of power in the ASIC designs at Ericsson. This Thesis focusses on developing a power analysis and reduction flow for the common memory controller by connecting the verification environment of the block to low-level power analysis tools, using motivated test cases to collect power metrics, thereby leading to two main goals of the Thesis, characterization and optimization of the block for power. This work also includes an energy efficiency perspective through the Differential Energy Analysis technique, initiated by Qualcomm and Ansys, to improve the flow by improving the test cases that help uncover power inefficiencies/bugs and therefore optimize the block. The flow developed in the Thesis fulfills the goals of characterizing and optimizing the block. The characterization data is presented to provide an idea of the type of data that can be collected and useful for SoC architects and designers in planning for future designs. The characterization/profiling data collected from the blocks collectively contribute to the Electronic System-level power analysis that helps correlate the ASIC power estimate to silicon. The work also validates the flow by working on a specific sub-block, identifying possible power bugs, modifying the design and validating improved performance and thereby, validating the flow. / Med FinFET-baserade applikationsspecifika integrerade kretsar (ASIC) -konstruktioner som ger löften om skalbarhet, prestanda och kraft är vägen framåt ojämn med tekniska utmaningar när det gäller att bygga effektiva ASIC: er. Formgivare kan inte längre lita på den "autoskalande" effektminskningen som följer teknisk nodskalning, i dessa tider då 7nm presenterar sig som en "långlivad" nod. Detta leder till behovet av tidig kraftanalys och reduktionsflöden som är integrerade i ASIC Intellectual Property (IP) designflöde. Detta leder till fokus på energieffektiv design förutom att det är funktionellt effektivt. Krafteffektivitetsrelaterade hotspots är de ledande orsakerna till respins av chip, och en riktlinjemetodik för att konstruera block på ett energieffektivt sätt leder till energieffektiv design av Integrated Circuits (ICs). Detta lindrar intensiteten hos kylbehovet och kostnaden. Common Memory-kontrollen är en av de ledande energikonsumenterna i ASIC-designen hos Ericsson. Denna avhandling fokuserar på att utveckla en effektanalys och reduktionsflöde för den gemensamma minneskontrollern genom att ansluta verifieringsmiljön för blocket till lågnivåeffektanalysverktyg, med hjälp av motiverade test caser för att samla effektmätvärden, vilket leder till två huvudmål för avhandlingen, karakterisering och optimering av blocket för kraft. Detta arbete inkluderar också energieffektivitetsperspektiv genom Differential Energy Analys-teknik, initierad av Qualcomm och Ansys, för att förbättra flödet genom att förbättra test cases som hjälper till att upptäcka effekteffektivitet / buggar och därför optimera blocket. Flödet som utvecklats i avhandlingen uppfyller målen att karakterisera och optimera blocket. Karaktäriseringsdata presenteras för att ge en uppfattning om vilken typ av data som kan samlas in och vara användbara för SoC-arkitekter och designers i planering för framtida mönster. Karaktäriserings/ profileringsdata som samlats in från blocken bidrar tillsammans till effektanalysen för elektronisk systemnivå som hjälper till att korrelera ASIC-effektberäkningen till kisel. Arbetet validerar också flödet genom att arbeta på ett specifikt underblock, identifiera möjliga effektbuggar, modifiera utforma och validera förbättrad prestanda och därmed validera flödet.

In this work, power supply noise contribution, at a particular node on the power grid, from clock/power gated blocks is maximized at particular time and the synthetic gating patterns of the blocks that result in the maximum noise is obtained for the interval 0 to target time. We utilize wavelet based analysis as wavelets are a natural way of characterizing the time-frequency behavior of the power grid. The gating patterns for the blocks and the maximum supply noise at the Point of Interest at the specified target time obtained via a Linear Programming (LP) formulation (clock gating) and Genetic Algorithm based problem formulation (Power Gating).

The unabated continuation of the Moore's law has allowed the doubling of the number of transistors per unit area of a silicon die every 2 years or so. At the same time, an increasing demand on consumer electronics and computing equipments to run sophisticated applications has led to an unprecedented complexity of hardware designs. These factors have necessitated the abstraction level of design-entry of hardware systems to be raised beyond the Register-Transfer-Level (RTL) to Electronic System Level (ESL). However, power envelope on the designs due to packaging and other thermal limitations, and the energy envelope due to battery life-time considerations have also created a need for power/energy efficient design. The confluence of these two technological issues has created an urgent need for solving two problems: (i) How do we enable a power-aware design flow with a design entry point at the Electronic System Level? (ii) How do we enable power aware High Level Synthesis to automatically synthesize RTL implementation from ESL? This dissertation distinguishes itself by addressing the following two issues: (i) Since power/energy consumption of electronic systems largely depends on implementation details, and high-level models abstract away from such details, power/energy estimation at such levels has not been addressed thoroughly. (ii) A lot of work has been done in applying various techniques on control-data-flow graphs (CDFG) to find power/area/latency pareto points during behavioral synthesis. However, high level C-based functional models of various compute-intensive components, which could be easily synthesized as co-processors, have many opportunities to reduce power. Some of these savings opportunities are traditional such as clock-gating, operand-isolation etc. The exploration of alternate granularities of these techniques with target applications in mind, opens the door for traditional power reduction opportunities at the high-level. This work therefore concentrates on the aforementioned two areas of inadequacy of hardware design methodologies. Our proposed solutions include utilizing ESL simulation traces and mapping those to lower abstraction levels for power estimation, derivation of statistical power models using regression based learning for power estimation at early design stages, etc. On the HLS front, techniques that insert the power saving features during the synthesis process using exploration of granularity and scope of clock-gating, sequential clock-gating are proposed. Finally, this work shows how to marry two domains, that is estimation and reduction. In this regard, a power model is proposed, which helps in predicting power savings obtained using clock-gating and further guiding HLS to selectively insert clock-gating. / Ph. D.

Due to the rapid development of semiconductor technology, the number of transistors of integrated circuits in unit area increases by double in roughly every two years. We then can add more circuits and functionality into a single chip. The size of electronic products certainly is reduced. Besides, because of the blooming popularity of wireless network standards in recently year, sensors have been wireless connected to provide more functionality and intelligence. They are, namely, wireless sensor network (WSN). Before long, the integrated circuit design will not only be emphasized on front-end circuits and hardware design, but also integration and functionality, which is so-called the system-on-chip (SOC) design. The first topic of this thesis is the implementation of IEEE 802.15.4 network prototype and hardware design. The main purpose of prototyping is to realize the highly portable IEEE 802.15.4 protocol stack library which can be quickly transferred to different hardwares. Thus, it shortens the time to market. In ASIC hardware design, we use WISHBONE bus as the interconnection architecture which can be easily integrated into current SOC design for an embedded system. The second topic is an application of IEEE 802.15.4 in medical monitoring, including system prototyping and ASIC hardware design, which collects the bladder pressure readings by a wireless link and ECG signals from our ASIC sensors. Finally, we realize the medical monitoring in a prototypical system.

The clock is the important synchronizing element in all synchronous digital systems. The difference in the clock arrival time between sink points is called the clock skew. This uncertainty in arrival times will limit operating frequency and might cause functional errors. Various clock routing techniques can be broadly categorized into 'balanced tree' and 'fixed mesh' methods. The skew and delay using the balanced tree method is higher compared to the fixed mesh method. Although fixed mesh inherently uses more wire length, the redundancy created by loops in a mesh structure reduces undesired delay variations. The fixed mesh method uses a single mesh over the entire chip but it is hard to introduce clock gating in a single clock mesh. This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate (SZF) and optimum number of transmission gates between sub-clock meshes (NTG) for 4x4 reconfigurable mesh, the average of the maximum skew for all benchmarks is reduced by 18.12 percent compared to clock mesh structure when no transmission gates are used between the sub-clock meshes (reconfigurable mesh with NTG =0). Further, the research deals with a ‘modified zero skew method' to connect synchronous flip-flops or sink points in the circuit to the clock grids of clock mesh. The wire length reduction algorithms can be applied to reduce the wire length used for a local clock distribution network. The modified version of ‘zero skew method’ of local clock routing which is based on Elmore delay balancing aims at minimizing wire length for the given bounded skew of CDN using clock mesh and H-tree. The results of ‘modified zero skew method' (HC_MZSK) show average local wire length reduction of 17.75 percent for all ISPD benchmarks compared to direct connection method. The maximum skew is small for HC_MZSK in most of the test cases compared to other methods of connections like direct connections and modified AHHK. Thus, HC_MZSK for local routing reduces the wire length and maximum skew.

Power dissipation is one of the major design issues of digital circuits. The power dissipated by a circuit affects its speed and performance. Multiplier is one of the most commonly used circuits in the digital devices. There are various types of multipliers available depending upon the application in which they are used. In the present thesis report, the importance of power dissipation in today's digital technology is discussed and the various types and sources of power dissipation have been elaborated. Different types of multipliers have been designed which vary in their structure and amount of power dissipation. The concept of pipelining is explained and the reduction in the power dissipation of the multipliers after pipelining is experimentally determined. Clock gating is a very important technique used in the design of digital circuits to reduce power dissipation. Various types of clock gating techniques have been presented as a case study. The technology used in the simulation of these circuits is 0.35µm CMOS and the simulator used is SPECTRE S.