La capacité actuelle d’accéder à des détecteurs très performants et de faible coût amène la communauté des concepteurs de systèmes optiques à un changement de paradigme. Plutôt que de réaliser des caméras généralistes, aptes à réaliser un grand nombre de missions d’observation différentes, il est maintenant de plus en plus courant de développer des systèmes imageurs adaptés à une seule mission et/ou à une seule classe d’objets. Prendre en compte ces connaissances a priori sur la scène et la mission, au moment de la conception, permet d’envisager des systèmes plus simples, mais aussi dotés de nouvelles compétences. L'objectif de la thèse est d'explorer les potentialités des tableaux non diffractants pour la conception de systèmes imageurs spécialisés. Pour cette étude nous considérons l'environnement des drones aéroportés de faible capacité d'emport pour lesquels les systèmes imageurs embarqués doivent être simples et robustes. Nous considérons de plus que la mission du système imageur est de détecter les obstacles. Pour cela, il doit délivrer une information 3D sur la scène observée. Dans un premier temps, j'ai analysé les propriétés d'imagerie du système imageur constitué d'un composant non diffractant et d'un détecteur matriciel. L'analyse comparative de deux composants, l'axicon et le tableau non diffractant, m'a permis de montrer que c'est le second composant qui est le mieux adapté pour remplir ce type de mission. J'ai ensuite réalisé un système imageur de démonstration, ce qui m'a permis au final de mettre en évidence sa capacité à faire de l'imagerie 3D. Cette étude a montré que les tableaux non diffractants ont un très fort potentiel pour réaliser un système imageur simple, robuste et dédié à l'imagerie 3D. Ce travail doit être poursuivi en partenariat avec des industriels pour appliquer la démarche de conception à une mission précise et transformer ce travail théorique en un système industrialisable. / Currently, detectors with high performances and a low cost are available and lead the community of optical designers to a new paradigm. Instead of designing generalist cameras, suitable for fulfilling a high number of different observation missions, it is now more and more common to develop imaging systems adapted to a unique mission and/or a unique object class. Taking this a priori knowledge on the observed scene or on the mission into account, at the beginning of the design process, allows us to consider simpler imaging systems with new properties. The aim of this thesis is to investigate the possibilities of nondiffracting array for the design of specialized imaging systems. For this study we consider the environment of unmanned aerial vehicles with a small payload capacity, for which embedded imaging systems must be simple and robust. We consider in addition that the mission of the imaging system is to detect obstacles. To do this, it must provide a 3D information on the observed scene. At first, I have analysed the properties of the imaging system composed by a nondiffracting optical device and a focal plane array. The comparison between two devices, axicon and nondiffracting arrays, allowed me to show that the second one is best suited for achieving this kind of mission. Then, I have made a practical implementation of such an imaging system. Finally, I have used it to demonstrate the 3D imaging property. This study has demonstrated the potential of nondiffracting array to design a simple and robust imaging system dedicated to 3D imaging. This work must be continued in partnership with the industry to apply the co-design process to a more precise mission, transforming this way this theoretical work into an industrial prototype.

Les communications entre les applications réseaux sont régies par un ensemble de règles regroupées sous forme de protocoles. Les messages protocolaires sont gérés par une couche de l’application réseau connue comme étant la couche de support protocolaire. Cette couche peut être de nature logicielle, matérielle ou conjointe. Cette couche se trouve à la frontière entre le coeur de l’application et le monde extérieur. A ce titre, elle représente un composant névralgique de l’application. Les performances globales de l’application sont ainsi directement liées aux performances de la couche de support protocolaire associée.Le processus de développement de ces couches consiste à traduire une spécification du protocole, écrite dans un langage de haut niveau tel que ABNF dans un langage bas niveau, logiciel ou matériel. Avec l’avènement des systèmes embarqués, de plus en plus de systèmes sur puce proposent l’utilisation de ressources matérielles afin d’accroître les performances des applicatifs. Néanmoins, peu de processus de développement de couches de support protocolaire tirent parti de ces ressources, en raison notamment de l’expertise nécessaire dans ce domaine.Cette thèse propose une approche générative conjointe logicielle-matérielle au développement du support protocolaire d’applications réseaux, pour améliorer leur performance tout en restant ergonomique pour le développeur de l’application. Notre approche est basée sur l’exploitation d’un langage dédié, appellé Zebra pour générer les différents composants logiciels et matériels formant la couche de support. L’expertise nécessaire est déportée dans l’utilisation du langage Zebra et les composants matériels générés permettent d’accroître les performances de l’application.Les contributions de cette thèse sont les suivantes : Nous avons effectué une analyse des protocoles et applications réseaux. Cette analyse nous a permis d’identifier les composants pour lesquels il est possible d’obtenir des gains de performances.Nous avons conçu et exploité un langage dédié, Zebra, permettant de décrire les différentes entités de la couche de support protocolaire et générant les éléments logiciels et matériels la composant. Nous avons construit un système sur puce exécutant un système d’exploitation Linux afin d’étayer notre approche. Nous avons conçu des accélérateurs matériels déployables pour différents protocoles réseaux sur ce système et pilotables par les applicatifs. Afin de rendre l’accès aux accélérateurs matériels transparent pour les applications réseaux, nous avons développé un intergiciel gérant l’ensemble de ces accès. Cet intergiciel permet à plusieurs applications et/ou à plusieurs clients d’une même application d’utiliser les accélérateurs pour le traitement des messages protocolaires. Nous avons évalué les performances de notre approche dans des conditions réelles. Nous avons comparé ces performances à celles de couches de supports faisant référence dans le domaine. Nous avons constaté un gain de performance conséquent pour l’approche que nous proposons. / Communications between network applications is achieved by using rulesets known as protocols. Protocol messages are managed by the application layer known as the protocol parsing layer or protocol handling layer. Protocol parsers are coded in software, in hardware or based on a co-design approach. They represent the interface between the application logic and the outside world. Thus, they are critical components of network applications. Global performances of network applications are directly linked to the performances of their protocol parser layers.Developping protocol parsers consists of translating protocol specifications, written in a high level language such as ABNF towards low level software or hardware code. As the use of embedded systems is growing, hardware ressources become more and more available to applications on systems on chip (SoC). Nonetheless, developping a network application that uses hardware ressources is challenging, requiring not only expertise in hardware design, but also a knowledge of the protocols involved and an understanding of low-level network programming.This thesis proposes a generative hardware-software co-design based approach to the developpement of network protocol message parsers, to improve their performances without increasing the expertise the developper may need. Our approach is based on a dedicated language, called Zebra, that generates both hardware and software elements that compose protocol parsers. The necessary expertise is deported in the use of the Zebra language and the generated hardware components permit to improve global performances.The contributions of this thesis are as follows : We provide an analysis of network protocols and applications. This analysis allows us to detect the elements which performances can be improved using hardware ressources. We present the domain specific language Zebra to describe protocol handling layers. Software and hardware components are then generated according to Zebra specifications. We have built a SoC running a Linux operating system to assess our approach.We have designed hardware accelerators for different network protocols that are deployed and driven by applications. To increase sharing of parsing units between several tasks, we have developped a middleware that seamlessly manages all the accesses to the hardware components. The Zebra middleware allows several clients to access the ressources of a hardware accelerator. We have conducted several set of experiments in real conditions. We have compared the performances of our approach with the performances of well-knownprotocol handling layers. We observe that protocol handling layers baded on our approach are more efficient that existing approaches.

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry. / Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria. / Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria.

Healthcare in Sweden are in need of a drastic change to meet the requirements of highly developed societies, and information technology is seen as an essential part to get there. However, the Swedish healthcare have to challenge their traditional innovation approaches as well. For example, it has become more common to engage patients in the innovation process through web-based platforms. We have been focusing on an approach called co-creation by studying a workshop, in which potential users and other stakeholders are cooperating creatively to come up with innovative solutions in order to improve healthcare practice. Our findings suggests that co-creation may increase the mutual understanding between different stakeholders, for example healthcare professionals and IT developers, enable horizontal learning through and outside the organization and also to raise concepts and actions that are responding to healthcare needs. However, we have found important challenges in bridging barriers that may occur when gathering people of different competencies, and involving proper participants that are representative of their groups.

abstract: The adoption of the Service Oriented Architecture (SOA) as the foundation for developing a new generation of software systems - known as Service Based Software Systems (SBS), poses new challenges in system design. While simulation as a methodology serves a principal role in design, there is a growing recognition that simulation of SBS requires modeling capabilities beyond those that are developed for the traditional distributed software systems. In particular, while different component-based modeling approaches may lend themselves to simulating the logical process flows in Service Oriented Computing (SOC) systems, they are inadequate in terms of supporting SOA-compliant modeling. Furthermore, composite services must satisfy multiple QoS attributes under constrained service reconfigurations and hardware resources. A key desired capability, therefore, is to model and simulate not only the services consistent with SOA concepts and principles, but also the hardware and network components on which services must execute on. In this dissertation, SOC-DEVS - a novel co-design modeling methodology that enables simulation of software and hardware aspects of SBS for early architectural design evaluation is developed. A set of abstractions representing important service characteristics and service relationships are modeled. The proposed software/hardware co-design simulation capability is introduced into the DEVS-Suite simulator. Exemplar simulation models of a communication intensive Voice Communication System and a computation intensive Encryption System are developed and then validated using data from an existing real system. The applicability of the SOC-DEVS methodology is demonstrated in a simulation testbed aimed at facilitating the design & development of SBS. Furthermore, the simulation testbed is extended by integrating an existing prototype monitoring and adaptation system with the simulator to support basic experimentation towards design & development of Adaptive SBS. / Dissertation/Thesis / Ph.D. Computer Science 2011

Visando atuação flexível em redes heterogêneas, modernos sistemas multimídia podem adotar o conceito da codificação escalável, onde o fluxo de vídeo é composto por múltiplas camadas, cada qual complementando e aprimorando gradualmente as características de exibição, de forma adaptativa às capacidades de cada receptor. Atualmente, a especificação H.264/SVC representa o estado da arte da área, por sua eficiência de codificação aprimorada, porém demanda recursos computacionais extremamente elevados. Neste contexto, o presente trabalho apresenta uma arquitetura de projeto colaborativo de hardware e software, que explora as características dos diversos algoritmos internos do codificador H.264/SVC, buscando um adequado balanceamento entre as duas tecnologias (hardware e software) para a implementação prática de um codificador escalável de até 16 camadas em formato de 1920x1080 pixels. A partir de um modelo do código de referência H.264/SVC, refinado para reduzir tempos de codificação, foram definidas estratégias de particionamento de módulos e integração entre entidades de software e hardware, avaliando-se questões como dependência de dados e potencial de paralelismo dos algoritmos, assim como restrições práticas das interfaces de comunicação e acessos à memória. Em hardware foram implementados módulos de transformadas, quantização, filtro anti-blocagem e predição entre camadas, permanecendo em software funções de gerência do sistema, entropia, controle de taxa e interface com usuário. A solução completa obtida, integrando módulos em hardware, sintetizados em uma placa de desenvolvimento, com o software de referência refinado, comprova a validade da proposta, pelos significativos ganhos de desempenho registrados, mostrando-se como uma solução adequada para aplicações que exijam codificação escalável tempo real. / In order to support heterogeneous networks and distinct devices simultaneously, modern multimedia systems can adopt the scalability concept, when the video stream is composed by multiple layers, each one being responsible for gradually enhance the video exhibition quality, according to specific receiver capabilities. Currently the H.264/SVC specification can be considered the state-of-art in this area, by improving the coding efficiency, but, in the other hand, impacting in extremely high computational demands. Based on that, this work presents a hardware/software co-design architecture, which explores the characteristics of H.264/SVC internal algorithms, aiming the right balancing between both technologies (hardware and software) in order to generate a practical scalable encoder implementation, able to process up to 16 layers in 1920x1080 pixels format. Based in an H.264/SVC reference code model, which was refined in order to reduce global encoding time, the approaches for module partitioning and data integration between hardware and software were defined. The proposed methodology took into account characteristics like data dependency and inherent possibility of parallelism, as well practical restrictions like influence of communication interfaces and memory accesses. Particularly, the modules of transforms, quantization, deblocking and inter-layer prediction were implemented in hardware, while the functions of system management, entropy, rate control and user interface were kept in software. The whole solution, which was obtained integrating hardware modules, synthesized in a development board, with the refined H.264/SVC reference code, validates the proposal, by the significant performance gains registered, indicating it as an adequate solution for applications which require real-time video scalable coding.

abstract: Coarse-grained Reconfigurable Arrays (CGRAs) are promising accelerators capable of accelerating even non-parallel loops and loops with low trip-counts. One challenge in compiling for CGRAs is to manage both recurring and nonrecurring variables in the register file (RF) of the CGRA. Although prior works have managed recurring variables via rotating RF, they access the nonrecurring variables through either a global RF or from a constant memory. The former does not scale well, and the latter degrades the mapping quality. This work proposes a hardware-software codesign approach in order to manage all the variables in a local nonrotating RF. Hardware provides modulo addition based indexing mechanism to enable correct addressing of recurring variables in a nonrotating RF. The compiler determines the number of registers required for each recurring variable and configures the boundary between the registers used for recurring and nonrecurring variables. The compiler also pre-loads the read-only variables and constants into the local registers in the prologue of the schedule. Synthesis and place-and-route results of the previous and the proposed RF design show that proposed solution achieves 17% better cycle time. Experiments of mapping several important and performance-critical loops collected from MiBench show proposed approach improves performance (through better mapping) by 18%, compared to using constant memory. / Dissertation/Thesis / Masters Thesis Computer Science 2016

Visando atuação flexível em redes heterogêneas, modernos sistemas multimídia podem adotar o conceito da codificação escalável, onde o fluxo de vídeo é composto por múltiplas camadas, cada qual complementando e aprimorando gradualmente as características de exibição, de forma adaptativa às capacidades de cada receptor. Atualmente, a especificação H.264/SVC representa o estado da arte da área, por sua eficiência de codificação aprimorada, porém demanda recursos computacionais extremamente elevados. Neste contexto, o presente trabalho apresenta uma arquitetura de projeto colaborativo de hardware e software, que explora as características dos diversos algoritmos internos do codificador H.264/SVC, buscando um adequado balanceamento entre as duas tecnologias (hardware e software) para a implementação prática de um codificador escalável de até 16 camadas em formato de 1920x1080 pixels. A partir de um modelo do código de referência H.264/SVC, refinado para reduzir tempos de codificação, foram definidas estratégias de particionamento de módulos e integração entre entidades de software e hardware, avaliando-se questões como dependência de dados e potencial de paralelismo dos algoritmos, assim como restrições práticas das interfaces de comunicação e acessos à memória. Em hardware foram implementados módulos de transformadas, quantização, filtro anti-blocagem e predição entre camadas, permanecendo em software funções de gerência do sistema, entropia, controle de taxa e interface com usuário. A solução completa obtida, integrando módulos em hardware, sintetizados em uma placa de desenvolvimento, com o software de referência refinado, comprova a validade da proposta, pelos significativos ganhos de desempenho registrados, mostrando-se como uma solução adequada para aplicações que exijam codificação escalável tempo real. / In order to support heterogeneous networks and distinct devices simultaneously, modern multimedia systems can adopt the scalability concept, when the video stream is composed by multiple layers, each one being responsible for gradually enhance the video exhibition quality, according to specific receiver capabilities. Currently the H.264/SVC specification can be considered the state-of-art in this area, by improving the coding efficiency, but, in the other hand, impacting in extremely high computational demands. Based on that, this work presents a hardware/software co-design architecture, which explores the characteristics of H.264/SVC internal algorithms, aiming the right balancing between both technologies (hardware and software) in order to generate a practical scalable encoder implementation, able to process up to 16 layers in 1920x1080 pixels format. Based in an H.264/SVC reference code model, which was refined in order to reduce global encoding time, the approaches for module partitioning and data integration between hardware and software were defined. The proposed methodology took into account characteristics like data dependency and inherent possibility of parallelism, as well practical restrictions like influence of communication interfaces and memory accesses. Particularly, the modules of transforms, quantization, deblocking and inter-layer prediction were implemented in hardware, while the functions of system management, entropy, rate control and user interface were kept in software. The whole solution, which was obtained integrating hardware modules, synthesized in a development board, with the refined H.264/SVC reference code, validates the proposal, by the significant performance gains registered, indicating it as an adequate solution for applications which require real-time video scalable coding.

Visando atuação flexível em redes heterogêneas, modernos sistemas multimídia podem adotar o conceito da codificação escalável, onde o fluxo de vídeo é composto por múltiplas camadas, cada qual complementando e aprimorando gradualmente as características de exibição, de forma adaptativa às capacidades de cada receptor. Atualmente, a especificação H.264/SVC representa o estado da arte da área, por sua eficiência de codificação aprimorada, porém demanda recursos computacionais extremamente elevados. Neste contexto, o presente trabalho apresenta uma arquitetura de projeto colaborativo de hardware e software, que explora as características dos diversos algoritmos internos do codificador H.264/SVC, buscando um adequado balanceamento entre as duas tecnologias (hardware e software) para a implementação prática de um codificador escalável de até 16 camadas em formato de 1920x1080 pixels. A partir de um modelo do código de referência H.264/SVC, refinado para reduzir tempos de codificação, foram definidas estratégias de particionamento de módulos e integração entre entidades de software e hardware, avaliando-se questões como dependência de dados e potencial de paralelismo dos algoritmos, assim como restrições práticas das interfaces de comunicação e acessos à memória. Em hardware foram implementados módulos de transformadas, quantização, filtro anti-blocagem e predição entre camadas, permanecendo em software funções de gerência do sistema, entropia, controle de taxa e interface com usuário. A solução completa obtida, integrando módulos em hardware, sintetizados em uma placa de desenvolvimento, com o software de referência refinado, comprova a validade da proposta, pelos significativos ganhos de desempenho registrados, mostrando-se como uma solução adequada para aplicações que exijam codificação escalável tempo real. / In order to support heterogeneous networks and distinct devices simultaneously, modern multimedia systems can adopt the scalability concept, when the video stream is composed by multiple layers, each one being responsible for gradually enhance the video exhibition quality, according to specific receiver capabilities. Currently the H.264/SVC specification can be considered the state-of-art in this area, by improving the coding efficiency, but, in the other hand, impacting in extremely high computational demands. Based on that, this work presents a hardware/software co-design architecture, which explores the characteristics of H.264/SVC internal algorithms, aiming the right balancing between both technologies (hardware and software) in order to generate a practical scalable encoder implementation, able to process up to 16 layers in 1920x1080 pixels format. Based in an H.264/SVC reference code model, which was refined in order to reduce global encoding time, the approaches for module partitioning and data integration between hardware and software were defined. The proposed methodology took into account characteristics like data dependency and inherent possibility of parallelism, as well practical restrictions like influence of communication interfaces and memory accesses. Particularly, the modules of transforms, quantization, deblocking and inter-layer prediction were implemented in hardware, while the functions of system management, entropy, rate control and user interface were kept in software. The whole solution, which was obtained integrating hardware modules, synthesized in a development board, with the refined H.264/SVC reference code, validates the proposal, by the significant performance gains registered, indicating it as an adequate solution for applications which require real-time video scalable coding.

Ce travail porte sur la conception d'un amplificateur de puissance à 79 GHz et la co-intégration de l'amplificateur de puissance et l'antenne en technologie silicium SiGe. L'objectif de la thèse est de développer un module radiofréquence à l'émission pour des applications radar à 79 GHz. Ce module sera composé d'un amplificateur de puissance, d'une antenne et du circuit d'adaptation PA/Antenne. L'inter-étage entre le PA et l'antenne est une source supplémentaire d'atténuation du signal, d‟autant plus rédhibitoire en technologie intégrée pour des fréquences aussi élevées. En réalisant une conception commune, ou co-design, de l'antenne et de l'amplificateur de puissance (PA), nous pouvons, à terme, nous affranchir du traditionnel inter-étage d'adaptation d'impédance entre ces deux blocs. Plus précisément, il convient de dimensionner l'antenne afin qu'elle présente a la sortie du PA l'impédance optimale que requiert son rendement en puissance maximum. / This work focuses on the design of a power amplifier (PA) at 79 GHz and the co-integration of the PA and the antenna on SiGe technology. The objective of this thesis is to develop a RF front-end block for radar applications at 79 GHz. This block is compound of a power amplifier, antenna and PA/Antenna inter-stage matching. The inter-stage between the PA and the antenna adds supplementary losses in the global performances, especially prohibitive in integrated technology for high frequencies. The co-design of the antenna and the PA allows to suppress the traditional inter-stage impedance matching between these two blocks. More specifically, it is suitable to design the antenna with the appropriate output impedance of the PA which gives optimal performances for maximum power and efficiency.