<p>This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain.</p>

This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer &amp; Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain.

L'objectif de ce travail était d’élaborer la brique de base d'un convertisseur analogique numérique supraconducteur à architecture pipeline, fonctionnant à 30GHz de fréquence d’échantillonnage. Ce convertisseur est constitué d’un bloc de N comparateurs disposés en cascade le long d’une ligne de transmission. Chaque étage de comparaison est constitué d'un SQUID rf mutuellement couplé à un tronçon de ligne de transmission. Lorsque le signal à convertir arrive à la hauteur d'un comparateur, il génère un champ magnétique qui induit un courant dans le SQUID rf. Ce courant pourra faire commuter la jonction Josephson du SQUID rf dans certains cas, en fonction des caractéristiques internes de la jonction Josephson du SQUID et de son environnement. La commutation, qui s’accompagne de l’apparition d’une impulsion de tension quantifiée SFQ, a été étudiée de manière théorique et expérimentale en fonction des différents paramètres du problème. / Superconductive analogue to digital converters (ADC) generally have speed and power dissipation advantages which should enable their application in telecommunication, medicine, and where an analogue signal (delivered e.g. by a sensor) needs to be digitized for post-processing.We are developing a new concept of analogue to digital converter using high critical temperature (Tc=90K) superconductors and operating at 30GHz; this converter is based an original structure, the pipeline architecture. The principle is to place a cascade of N comparators along a transmission line on which propagates the up-converted analogue signal. The carrier frequency is used in this case as a sampling signal.Each comparator, made with a SQUID loop, produces one bit at the carrier frequency: it codes the input signal by generating or not an RSFQ pulse (respectively "1” or “0"), and passes the residue (attenuated signal) in the following comparator.Here, we present steps for the comparator optimisation and mask design.Besides simulation results, we present the measurements at 30GHz carrier frequency of the comparator designed at low critical temperature (LTS). Finally, we suggest other tools to develop the optimised low critical temperature converter and we proposed the concept of the comparator operating at high critical temperature (HTS).

Abstract Dissertation deals with theoretical concepts and providing the basis for the use of forms of financing and acquisition of public goods and services through partnerships between the public and private sectors, as well as PPP (Public Private Partnership). Suitability PPP project in this work is assessed primarily in terms of developing a new methodology for evaluating projects. The theoretical part of the thesis aims to clarify the issue of PPPs in the context of regional and local regional development theories, principles and mechanisms of PPP legislative and institutional backing of the PPP, clarify the distinction between PPP and public procurement procedures and current assessment of PPP projects. The practical part focuses on the development of a methodology using a selection of qualitative and quantitative methods for evaluating investments and to form a complex output that will clearly and distinctly testify about the appropriateness of using the PPP method. For this purpose it is used in work processes, which are normally used for business valuation-generators values, property valuation, yield valuation, valuation based on market analysis, combining technologies and their incorporation / recast in the current assessment methodology, which is based on a Public Sector Comparator and determinants of value for money

This diploma thesis analyses and elaborates a methodical tool for evaluating the advantage of realization of construction of road infrastructure in the form of a PPP project. Furthermore this tool is subsequent applied to a particular project. The introductory part summarizes the basic theoretical knowledge regarding the project financing in the form of public-private partnerships. In the following part, a methodological tool for comparing the value for money based on different methods of realization. In the last part of the diploma thesis, this methodical tool is applied to a specific project, including a basic feasibility study.

The thesis is focused on the research and development of a new hybrid one-wire bus with special use enabling microelectronic integration. The bus, its physical layer and protocol have been developed based on applied research to meet the complex requirements of a new application group. These requirements are especially laid on the bus robustness and its immunity to interference and to work under real operating conditions. Part of the thesis is a description of existing solutions of one-wire buses, definition of current solutions and setting of goals for research of the new bus. Further are made the design of protocol and operating parameters of the bus operating in low power and power mode. In conclusion, the thesis deals with the practical verification of the proposed solution and there is also suggested a perspective of follow-up research in this area.

This works focusesof the propose and realization device for drive four quadrant bridge convertor with transistors IGBT. Final propose include drive unipolar and bipolar, choice between direct or alternative modulation.

<p>U ovoj doktorskoj disertaciji prikazana je koncepcija, realizacija i potvrda nove metode<br />jednovremenog etaloniranja strujnih mernih transformatora sa dve različite merne<br />aparature. Pregledom stručne literature ne postoji podatak da je ova metoda ranije<br />primenjivana. U disertaciji su prikazane različite merne metode za ispitivanje i<br />etaloniranje mernih transformatora koje imaju primenu u savremenoj praksi i koje<br />podrazumevaju i različite merne mogućnosti. Takođe je i ekperimentalno potvrđeno<br />jednovremeno ispitivanje i etaloniranje strujnih mernih transformatora sa nekoliko<br />mernih aparatura koje su zasnovane na različitim metodama. Sprovedna istraživanja i<br />eksperimentalni rezultati pokazuju i potvrđuju niz prednosti ovakvog načina<br />etaloniranja. Detaljna analiza komponenti merne nesigurnosti pokazala je da se<br />primenom ove metode postiže poboljšanje merne nesigurnost etaloniranja za skoro red<br />veličine u odnosu na klasično pojedinačno etaloniranje sa dve različite merne<br />aparature. Analiza uticajnih veličina na mernu nesigurnost pokazuje da se po ovoj novoj<br />metodi etaloniranja eliminiše niz komponenti od kojih su najznačajnije: uticaj<br />nejednakosti referentnih struja i ispitnog opterećenja. Istraživanja su takođe pokazala<br />da jednovremena metoda osim što doprinosi podizanju tačnosti etaloniranja strujnih<br />transformatora, ima primenu i u etaloniranju mernih aparatura za ispitivanje tačnosti<br />mernih transformatora i interkonparaciji strujnih etalon transformatora. Kroz<br />konkretne primere realizovane u praksi, razmotreni su i prikazani načini etaloniranja<br />mernih aparatura za ispitivanje tačnosti ovom novom metodom. Interkomparacijom dva<br />merna sistema visoke klase tačnosti Nacionalnog merološkog instituta Kanade<br />(National Research Council Canada), od kojih je jedna razvijena u Elektrotehničkom<br />Institutu &quot;Nikola Tesla&quot;, pokazana je i prednost primene jednovremene metode u oblasti<br />primarne metrologije strujnih mernih transformatora.</p> / <p>The dissertation presents the concept, its realisation and verification of the new method<br />of simultaneous comparison of the current transformers by two different measuring<br />apparatus. It is shown by searching the literature, that this method has not been used<br />before. In this dissertation different measuring methods for testing and calibration of<br />current transformers, with their different measuring capabilities are presented. Most of<br />them have been used in recent practice. Furthermore, the experimental verification of<br />new simultaneous calibration method is presented. For this reason some measuring<br />apparatus based on different measuring methods were used. Conducted research and<br />experimental results confirmed a number of advantages of this calibration method.<br />Detailed analysis of the components of the uncertainty of measurements shown that<br />using simultaneous method uncertainty of measurements have been improved<br />comparing to method with two individual calibration by different apparatus. In that case<br />some of the measuring uncertainty components can be neglected. The most significant<br />is component caused by variation of referent current and component caused by variation<br />of burden. The research has also showed that simultaneous method can be used for<br />calibration of measuring apparatus for current transformer accuracy testing and their<br />inter-comparisons. The ways of calibration of apparatus for current transformer accuracy<br />testing are considered and presented, through concrete examples realized in practice.<br />A high-accuracy comparison of two NRC (National Research Council Canada)<br />calibration systems were carried out by new simultaneous method. One measuring<br />system is developed at Electrical Engineering institute Nicola Tesla, Belgrade.<br />Accordingly the advantage of simultaneous method applied at the primary metrology of<br />current transformer is verified.</p>

No description available.

[pt] Os sistemas de múltiplas entradas e múltiplas saídas (MIMO) empregam um número crescente de antenas, o que leva a relevantes consumo de energia e custo de hardware dos front-ends correspondentes. Nesse contexto, o uso de conversores analógico-digitais (ADCs) de baixa resolução é promovido como uma solução promissora para este problema. Neste estudo consideramos um receptor MIMO de baixa resolução que implica que os sinais recebidos são processados simultaneamente pelos 1-bit ADCs e pela rede comparadora. Os sinais de entrada da rede comparadora podem vir de antenas diferentes, de modo que a extensão da rede comparadora pode ser interpretada como canais virtuais com saídas binárias. Com base nesses receptores MIMO de baixa resolução, desenvolvemos um estimador de canal e detector lineares de baixa resolução baseados no critério de mínimo erro médio quadrático (LRA-LMMSE) de acordo com o teorema de Bussgang. Duas redes de comparação são propostas, nomeadas, redes total e parcialmente conectadas. Também desenvolvemos uma rede parcialmente conectada baseada em busca gananciosa que usa muito menos comparadores para obter um desempenho bem próximo ao da rede totalmente conectada. Os resultados numéricos mostram que adicionar canais virtuais pode ser melhor do que adicionar canais físicos extras que correspondem a antenas de recepção adicionais em termos de taxa de erro de bit (BER). Além disso, ao empregar o estimador de canal proposto e seu erro de estimativa correspondente, construímos um limite inferior na taxa de soma ergódica para o receptor LRA-MMSE. Os resultados de simulação mostram que os sistemas com a proposta sistemas MIMO auxiliados por rede com quantização de 1-bit no receptor superam o convencional sistema MIMO de 1-bit em termos de desempenho de BER e erro quadrático médio (MSE). Além disso, as simulações numéricas confirmam uma vantagem significativa em termos de taxa de soma para o sistema proposto. / [en] Multiple-input multiple-output (MIMO) systems employs an increasing number of antennas, which leads to relevant energy consumption and hardware cost of the corresponding front ends. In this context, the use of lowresolution analog to digital converters (ADCs) is promoted as a promising solution to this problem. In this study we consider a low-resolution MIMO receiver which implies that the received signals simultaneously are processed by the 1-bit ADCs and the comparator network. The input signals for the comparator network can come from different antennas, such that the comparator network extension can be interpreted as virtual channels with binary outputs. Based on such low-resolution MIMO receivers, we develop low-resolution aware linear minimum mean-squared error (LRA-LMMSE) channel estimator and detector according to the Bussgang theorem. Two comparator networks are proposed, namely, fully and partially connected networks. We also devise a greedy search-based partially connected network that can use much less comparators to approach the performance of the fully connected network. Numerical results shows that adding virtual channels can be better than adding extra physical channels which corresponds to additional receive antennas in terms of bit error rate (BER). Furthermore, by employing the proposed channel estimator and its corresponding estimation error, we build up a lower bound on the ergodic sum rate for the LRA-LMMSE receiver. Simulation results show that the systems with the proposed network-aided MIMO systems with 1-bit quantization at the receiver outperforms the conventional 1-bit MIMO system in terms of BER and mean-square error (MSE) performances. Moreover, numerical simulations confirm a significant advantage in terms of sum rate for the proposed system.