Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 100-105). Also available in electronic version. Access restricted to campus users.

Thesis (M.S.)--Rochester Institute of Technology, 2005. / Typescript. Includes bibliographical references (leaves 84-86).

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references. Also available in electronic version.

This study uses differential pass transistor methodology for implementing and evaluating Boolean functions. The main goal is investigation of CMOS and nMOS approaches in pass transistor logic design. Pass-transistor logic is most effective in the implementation of Boolean functions when the vectors are in the same format. It has been demonstrated that nMOS pass transistor logic driven by a control signal voltage above the V dd level offers a significant improvement in speed. nMOS pass transistorsalso offer less area consumption in comparison to the CMOS approach. The philosophy developed here has been used in the design of a program for the layout generation of pass transistor networks. This program has been applied to the design of a 4-to-1 multiplexer and an adder (sum and carry). The layout of the circuit sub-cell have been done using the program Magic, based on 3μ CMOS p-well technology.

Radio-frequency filters and oscillators are widely used in wireless communication and high-speed digital systems, and they are mostly built on passive integrated inductors, which occupy a relative large silicon area. This research attempted to implement filters and oscillators operating at 1-5 GHz using transistors only, to reduce the circuits’ area. The filters and oscillators are designed using active inductors, based on the gyrator principle; they are fabricated in standard digital CMOS technology to be compatible with logic circuits and further lower the cost. To obtain the highest operating frequency, only parasitic capacitors were used. Two new active-inductor circuits are derived from this research, labeled allNMOS and all-NMOS-II. The all-NMOS active inductor was used to design high-Q bandpass filters and oscillators, which were fabricated in TSMC’s 0.18-µm digital CMOS process. The highest center frequency measured was 5.7 GHz at 0.20-µm gate length and the maximum repeatably measured Q was 665. 2.4-GHz circuits were also designed and fabricated in 0.40-µm gate length. The all-NMOS-II circuit has superior linearity and signal fidelity, which are robust against process and temperature variations, due to its novel structure. It was used in signal drivers and will be fabricated in commercial products. Small-signal analysis was conducted for each of the active-inductor, filter and oscillator circuits, and the calculated performance matches those from simulations. The noise performance of the active inductor, active-inductor filter and oscillator was also analyzed and the calculated results agree with simulations. The difference between simulation and measured results is about 10% due to modeling and parasitic extraction error. The all-NMOS active-inductor circuit was granted a US patent. The US patent for all-NMOS-II circuit is pending. This research generated three conference papers and two journal papers.

Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.

En dépit du développement rapide de la médecine, les maladies cardiovasculaires restent la première cause de mortalité dans le monde. En France, chaque année, plus de 50 000 personnes meurent subitement en raison d'arythmies cardiaques. L'identification des patients à risque élevé de décès soudain est toujours un défi. Pour détecter les arythmies cardiaques, actuellement Holter est généralement utilisé pour enregistrer les signaux électrocardiogramme (ECG) à 1~3 dérivations pendant 24h à 72h. Cependant l'utilisation de Holter est limitée parmi la population en raison de son encombrement (pas convivial) et de son coût. Un Holter mono puce portable nommé SoC-Holter qui permet d'enregistrer 1 à 4 dérivations est introduit. Le déploiement d'un réseau de capteurs sans fil exige que chaque SoC-Holter soit peu encombrant et peu cher, et consomme peu d’énergie. Afin de minimiser la consommation d'énergie et le coût du système, la technologie Complementary Metal Oxide Semiconductor (CMOS) (0.35μm) est utilisée pour la première implémentation de SoC-Holter. Puis une nouvelle méthode de détection basée sur Acquisition Comprimée (CS) est introduite pour résoudre les problèmes de consommation d'énergie et de capacité de stockage de SoC-Holter. Le principe premier de cette plate-forme est d'échantillonner les signaux ECG sous la fréquence de Nyquist ‘sub-Nyquist’ et par la suite de classer directement les mesures compressées en états normal et anormal. Minimiser le nombre de fils qui relient les électrodes à la plate-forme peut rendre l’utilisateur de SoC-Holter plus confortable, car deux électrodes sont très proches sur la surface du corps. La différence ECG enregistrée est analysée à l'aide de Vectocardiogramme (VCG). Les résultats expérimentaux montrent qu'une approche intégrée, à faible coût et de faible encombrement (SoC-Holter) est faisable. Le SoC-Holter consomme moins de 10mW en fonctionnement. L'estimation des paramètres du signal acquis est effectuée directement à partir de mesures compressées, éliminant ainsi l'étape de la reconstruction et réduisant la complexité et le volume des calculs. En outre, le système fournit les signaux ECG compressés sans perte d'information, de ce fait il réduit significativement la consommation d'énergie pour l'envoi de message et l’espace de stockage mémoire. L'effet de placement des électrodes est évalué sur la QRS complexe lorsqu'il a enregistré avec deux électrodes adjacentes. La méthode est basée sur l'algorithme de ‘QRS-VCG loop alignment’. La méthode moindre carré est utilisée pour estimer la corrélation entre une boucle VCG observée et une boucle de référence en respectant les transformations de rotation et la synchronisation du temps. Les emplacements d'électrodes les moins sensibles aux interférences sont étudiés. / According to the figures released by World Health Organization (WHO), cardiovascular disease is the number one cause of death in the world. In France every year more than 50,000 people die suddenly due cardiac arrhythmias. Identification of high risk sudden death patients is still a challenge. To detect cardiac arrhythmias, currently Holter is generally used to record 1~4 leads electrocardiogram (ECG) signals during 24h to 72h. However the use of Holter is limited among the population due to its form factor (not user-friendly) and cost. An integrated single chip wearable Holter named SoC-Holter that enables to record 1 to 4 leads ECG is introduced. Deployment of wireless sensor network requires each SoC-Holter with less power consumption, low-cost charging system and less die area.To minimize energy consumption and system cost, Complementary Metal Oxide Semiconductor (CMOS) technology (0.35μm) is used to prototype the first implementation of SoC-Holter. Then a novel method based on Compressed Sensing (CS) technique is introduced for solving the problems of power consumption and storage capacity of SoC-Holter. The main principle underlying this framework is to sample analog signals at sub-Nyquist rate and to classify directly compressed measurement into normal and abnormal state. Minimizing the wire connected electrodes to the platform can make the carrier more comfortable because two electrodes are attached closely on the surface of the body. Recording difference ECG is analyzed using Vectorcardiogram (VCG) theory. Experimental results show that an integrated, low cost, and user-friendly SoC-Holter is feasible. SoC-Holter consumes less than 10mW while the device is operating. It takes advantage of estimating parameters directly from compressed measurements, thereby eliminating the reconstruction stage and reducing the computational complexity on the platform. In addition, the framework provides compressed ECG signals without loss of information, reducing significantly the power consumption for message sending and memory storage space. The effect of electrode placement is evaluated by estimating QRS complex in recorded ECG signals by two adjacent electrodes. The method is based on the QRS-VCG loop alignment algorithm that estimates Least Square (LS) between an observed VCG loop and a reference loop with respect to the transformations of rotation and time synchronization. The electrode location with less sensitive to interference is investigated.

Three-Dimensional (3D) optical range-imaging is a field experiencing rapid growth, expanding into a wide variety of machine vision applications, most recently including consumer gaming. Time of Flight (ToF) cameras, akin to RADAR with light, sense distance by measuring the round trip time of modulated Infra-Red (IR) illumination light projected into the scene and reflected back to the camera. Such systems generate 'depth maps' without requiring the complex processing utilised by other 3D imaging techniques such as stereo vision and structured light. Existing range-imaging solutions within the ToF category either perform demodulation in the analogue domain, and are therefore susceptible to noise and non-uniformities, or by digitally detecting individual photons using a Single Photon Avalanche Diode (SPAD), generating large volumes of raw data. In both cases, external processing is required in order to calculate a distance estimate from this raw information. To address these limitations, this thesis explores alternative system architectures for ToF range imaging. Specifically, a new pixel concept is presented, coupling a SPAD for accurate detection of the arrival time of photons to an all-digital Phase- Domain Delta-Sigma (PDΔΣ) loop for the first time. This processes the SPAD pulses locally, converging to estimate the mean phase of the incoming photons with respect to the outgoing illumination light. A 128×96 pixel sensor was created to demonstrate this principle. By incorporating all of the steps in the range-imaging process – from time resolved photon detection with SPADs, through phase extraction with the in-pixel phase-domain ΔΣ loop, to depth map creation with on-chip decimation filters – this sensor is the first fully integrated 3D camera-on-achip to be published. It is implemented in a 130nm CMOS imaging process, the most modern technology used in 3D imaging work presented to date, enabled by the recent availability of a very low noise SPAD structure in this process. Excellent linearity of ±5mm is obtained, although the 1σ repeatability error was limited to 160mm by a number of factors. While the dimensions of the current pixel prevent the implementation of very high resolution arrays, the all-digital nature of this technique will scale well if manufactured in a more advanced CMOS imaging process such as the 90nm or 65nm nodes. Repartitioning of the logic could enhance fill factor further. The presented characterisation results nevertheless serve as first validation of a new concept in 3D range-imaging, while proposals for its future refinement are presented.

Today a growing number of applications in design engineering, production and environmental testing, and system service require specific analog waveforms and digital patterns. Such requirements are neither satisfactorily nor easily met by the use of standard function or single purpose, custom generators. Traditional methods of waveform generation suffer from undesirable complexity or mediocre performance and are otherwise limited. For the majority of arbitrary waveform generation applications, including medical engineering, modal analysis and electronic engineering, direct digital synthesis techniques are satisfactory. Direct digital synthesis, based generally on periodic retrieval of predetermined amplitude values, may be used to 2 generate such waveforms. Within the limits imposed by the system's maximum sample rate and the Nyquist criteria, any waveform may be produced using these techniques. The objective of this inquiry, within a particular set of constraints, is to extend the cost/performance envelope of direct digital synthesis techniques for the generation of arbitrary waveforms. Performance is enhanced, particularly in the areas of output bandwidth and signal purity.

Scaling down of the CMOS technology requires thinner gate dielectric to maintain high performance. However, due to the depletion of poly-Si gate, it is difficult to reduce the gate thickness further especially for sub-65 nm CMOS generation. Fully silicidation metal gate (FUSI) is one of the most promising solutions. Furthermore, FUSI metal gate reduces gate-line sheet resistance, prevents boron penetration to channels, and has good process compatibility with high-k gate dielectric. Poly-SiGe gate technology is another solution because of its enhancement of boron activation and compatibility with the conventional CMOS process. Combination of these two technologies for the formation of fully germanosilicided metal gate makes the approach very attractive. In this paper, the deposition of undoped Poly-Si₁₋xGex (0 < x < 30% ) films onto SiO₂ in a low pressure chemical vapor deposition (LPCVD) system is described. Detailed growth conditions and the characterization of the grown films are presented. / Singapore-MIT Alliance (SMA)