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Energetic particles from cosmic ray or terrestrial sources can strike sensitive areas of CMOS devices and cause soft errors. Understanding the effects of such interactions is crucial as the device technology advances, and chip reliability has become more important than ever. Particle accelerator testing has been the standard method to characterize the sensitivity of chips to single event upsets (SEUs). However, because of their costs and availability limitations, other techniques have been explored. Pulsed laser has been a successful tool for characterization of SEU behavior, but to this day, laser has not been recognized as a comparable method to beam testing. In this thesis, I propose a methodology of correlating laser soft error rate (SER) to particle beam gathered data. Additionally, results are presented showing a temperature dependence of SER and the "neighbor effect" phenomenon where due to the close proximity of devices a "weakening effect" in the ON state can be observed.

Legislative reforms aimed at slowing growth of US healthcare costs are focused on achieving greater value, defined specifically as health outcomes achieved per dollar spent. To increase value while payments are diminishing and tied to individual outcomes, healthcare must improve at predicting risks and outcomes. One way to improve predictions is through better modeling methods. Current models are predominantly based on logistic regression (LR). This project applied Reconstructability Analysis (RA) to data on hip and knee replacement surgery, and considered whether RA could create useful models of outcomes, and whether these models could produce predictions complimentary to or even stronger than LR models. RA is a data mining method that searches for relations in data, especially non-linear and higher ordinality relations, by decomposing the frequency distribution of the data into projections, several of which taken together define a model, which is then assessed for statistical significance. The predictive power of the model is expressed as the percent reduction of uncertainty (Shannon entropy) of the dependent variable (the DV) gained by knowing the values of the predictive independent variables (the IVs). Results showed that LR and RA gave the same results for equivalent models, and showed that exploratory RA provided better models than LR. Sixteen RA predictive models were then generated across the four DVs: complications, skilled nursing discharge, readmissions, and total cost. While the first three DVs are nominal, RA generated continuous predictions for cost by calculating expected values. Models included novel comorbidity variables and non-hypothesized interaction terms, and often resulted in substantial reductions in uncertainty. Predictive variables consisted of both delivery system variables and binary patient comorbidity variables. Complications were predicted by the total number of patient comorbidities. Skilled nursing discharges were predicted both by patient-related factors and delivery system variables (location, surgeon volume), suggesting practice patterns influence utilization of skilled nursing facilities. Readmissions were not well predicted, suggesting the data used in this project lacks the right variables or that readmissions are simply unpredictable. Delivery system variables (surgeon, location, and surgeon volume) were found to be the predominant predictors of total cost. Risk ratios were generated as an additional measure of effect size. These risk ratios were used to classify the IV states of the models as indicating higher or lower risk of adverse outcomes. Some IV states showed nearly 25% of patients at increased risk, while other IV states showed over 75% of patients at decreased risk. In real time, such risk predictions could support clinical decision making and custom-tailored utilization of services. Future research might address the limitations of this project's data and employ additional RA techniques and training-test splits. Implementation of predictive models is also discussed, with considerations for data supply lines, maintenance of models, organizational buy-in, and the acceptance of model output by clinical teams for use in real-time clinical practice. If outcomes and risk are adequately predicted, areas for potential improvement become clearer, and focused changes can be made to drive improvements in patient care. Better predictions, such as those resulting from the RA methodology, can thus support improvement in value--better outcomes at a lower cost. As reimbursement increasingly evolves into value-based programs, understanding the outcomes achieved, and customizing patient care to reduce unnecessary costs while improving outcomes, will be an active area for clinicians, healthcare administrators, researchers, and data scientists for many years to come.

Orientador: Jacobus Willibrordus Swart / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-12T18:12:37Z (GMT). No. of bitstreams: 1 Campos_FernandodeSouza_D.pdf: 2206636 bytes, checksum: f20b690f268876e5aef018b4b97266ac (MD5) Previous issue date: 2008 / Resumo: O trabalho apresentado nesta tese endereça dois importantes desafios impostos pela evolução da tecnologia CMOS, a diminuição da responsividade das junções e a redução da tensão de alimentação. Um fotodetector de alta responsividade e um sistema de imagem CMOS multiamostrado no domínio do tempo são propostos nesta tese. Como fototransistor de elevada responsividade propõem-se nesta tese o uso do Transistor Bipolar Lateral Controlado por Porta (GC-LBJT) operando como fototransistor de 4 terminais. Apresenta-se a análise do princípio de funcionamento e o desenvolvimento de um circuito equivalente CC. A fotoresposta do GC-LBJT é investigada em duas diferentes configurações, coletor-comum com tensão porta-base constante e emissor-comum com tensão porta-emissor constante. A característica da fotoresposta é associada às equações do dispositivo em ambas as configurações mostrando os principais parâmetros do dispositivo que determinam o ganho. Na configuração coletor-comum, a característica da fotoresposta varia de aproximadamente linear a sublinear por meio da tensão de controle VGB. Na configuração emissor-comum, o dispositivo apresenta fotoresposta sublinear e baixa excursão para toda faixa de tensão de controle (VGB) utilizada. Explorando a característica controlável do GC-LBJT em ambas as configurações, o fototransistor GC-LBJT pode apresentar ganho e responsividade maiores do que 10+6 e 10+4 A/W respectivamente. Propõe-se o método de múltipla-amostragem para sistemas de imagem CMOS no domínio do tempo. O pixel é composto por um comparador e um circuito de memória de um bit. O método de múltipla-amostragem no domínio do tempo permite reduzir o circuito de memória integrado ao pixel de 8 bits tipicamente para um único bit. O resultado da amostra armazenado na memória de um bit no pixel é lida externamente de forma síncrona e o valor do sinal do pixel é codificado de acordo com o instante da amostra no tempo. O número de bits e a velocidade de operação do circuito limitam a dimensão máxima da matriz. Além disso, este trabalho apresenta a influência da não-linearidade da capacitância do fotodiodo na característica da fotoresposta dos sistemas de imagem CMOS no domínio do tempo. Estudo do comportamento do ruído de padrão fixo e o temporal em sistema de imagem no domínio do tempo também são apresentados / Abstract: This thesis adresses two important challenges imposed by CMOS technology trends, the reduction of the junctions's responsivity and voltages levels. A new photodetector with high responsivity and a multi-sampling time domain image system are investigated. This thesis proposes to use the gate controlled lateral bipolar junction transistor (GCLBJT) as a four terminal phototransistor as photodetector with high responsivity. This work presents the photopolarization principle, gain current mechanism of the GC-LBJT in conjuction with DC equivalent circuit development. The GC-LBJT photo response is analysed in two different configurations, common colector with constant gate-base voltage and common emmiter with constant gate-emitter voltage. The photoresponse is related to device equations in both configurations. In the common colector with constant gate-base voltage configuration the photo response characteristic changes from linear to sublinear according to the VGB control voltage. In the common emmiter configuration, the device presents sublinear photo response and small changes for full range of the VGB control voltage used. Exploring the GC-LBJT controllable characteristic, the GC-LBJT phototransistor presents high and controllable gain all over the range of irradiation used, for both configurations. The multi-sampling method for time domain CMOS image systems is proposed. The pixel's architecture is composed by a comparator and a single bit memory circuit. The multisampling method in time-domain allows reducing memory circuits integrated per pixel with eight bit tipically to a single bit. The sample result stored in the single bit memory of the pixel is externally read in a synchronous way and the pixel signal value is coded according to the sampling instant. The number of the bits and the speed of circuit's operation define the upper limit of the matrix size. In addition, this work presents the influence of non-linearity on photoresponse characteristic for systems operating in time domain. The behavior of fixed and temporal pattern noise study in time domain image system is also presented / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-08T17:33:52Z (GMT). No. of bitstreams: 1 Agostinho_PetersonRibeiro_M.pdf: 4830694 bytes, checksum: d3db6a2118db3df2774037e49df52865 (MD5) Previous issue date: 2006 / Resumo: Este trabalho descreve o procedimento de projeto de amplificadores operacionais rail-to-rail em tecnologia CMOS. Para isto, foram objetos desse processo quatro configurações distintas. As quatro topologias utilizam estágio de entrada rail-to-rail com controle de gm e estágio de saída classe-AB com controle de corrente quiescente. Como especificação para as três primeiras configurações estão tensão de alimentação de ± 0.9V, ganho de manha aberta em baixas freqüências de 60dB e freqüência de ganho unitário de 4MHz para uma carga externa de 10k? em paralelo com 10pF. A quarta configuração é uma nova topologia adaptada para que os transistores operem na região de inversão fraca, com o objetivo de reduzir o consumo de potência. Como especificação para esta configuração temos tensão de alimentação de ± 0.75V e minimização do consumo de potência. Os resultados obtidos a partir dos protótipos fabricados em tecnologia CMOS 0.35µm foram próximos às especificações. Uma placa de circuito impresso foi implementada para caracterização dos amplificadores e, além disso, foi utilizado nessa placa um amplificador comercial para realizar comparações / Abstract: This dissertation describes the process of designing rail-to-rail operational amplifiers in CMOS technology. To accomplish this, the author focused on four distinct structures. The four topologies have rail-to-rail input stage with gm-control circuit and Class-AB output stage with quiescent-current control. The specification of three configurations included the nominal power supply of ± 0.9V, minimum open-loop low-frequency gain of 60dB and unity-gain frequency of 4MHz driving an external load of 10k? in parallel with 10pF. The fourth one is a new topology adapted to operate with transistors in weak inversion, in order to decrease the power consumption. The specification included nominal power supply of ± 0.75V and minimization of power consumption. Prototypes of the amplifiers were fabricated in 0.35µm CMOS technology and the results were in good agreements with the specifications. A printed circuit board was implemented to test the amplifiers and, additionally, was inserted a commercial amplifier, to make comparisons / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level. We argue that a bottom-up self-assembled fabric of nodes will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. The goal of this thesis is to evaluate the performance and cost of a self-configurable computing architecture composed of simple reconfigurable nodes for unstructured and unknown fabrics. We built a software and hardware framework for this purpose. The framework enables creating an irregular network of compute nodes where each node can be configured as a simple 2-input, 4-bit logic gate. The compute nodes are organized hierarchically by sending a packet through a top anchor node that recruits compute nodes with a chemically-inspired algorithm. The nodes are then self-configured by means of a gate-level netlist describing any digital logic circuit. A topology-agnostic optimization algorithm inspired by simulated annealing is then initiated to self-optimize the circuit for latency. Latency comparisons between non-optimized, brute-force optimized and our optimization algorithm are made. We further implement the architecture in VHDL and evaluate hardware cost, area, and energy consumption. The simple on-chip topology-agnostic optimization algorithm we propose results in a significant (up to 50\%) performance improvement compared to the non-optimized circuits. Our findings are of particular interest for emerging nano and molecular-scale circuits.

With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation. We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM). To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets. Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.

The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. Rapid progress in silicon VLSI technologies has made it possible to implement multi-function and high performance electronic circuits on a single die. Coupled with this, the need for interfacing digital blocks to the external world resulted in the integration of analog blocks such as A/D and D/A converters, filters and oscillators with the digital logic on the same die. Thus, mixed signal system-on-chip (SOC) solutions are becoming a common practice in the present day integrated circuit (IC) technologies. In digital domain, aggressive technology scaling redefines, in many ways, the role of interconnects vis-`a-vis the logic in determining the overall performance. Apart from signal integrity, power dissipation and reliability issues, delays over long interconnects far exceeding the logic delay becomes a bottleneck in high speed operation. Moreover, with an increasing density of chips, the number of interchip connections is greatly increased as more and more functions are put on the same chip; thus, the size and performance of the chip are mostly dominated by wiring rather than devices. One of the most promising approaches to solve the above interconnection problems is the use of multiple-valued logic (MVL) inside the chip [Han93, Smi88]. The number of interconnections can be directly reduced with multiple valued signal representation. The reduced complexity of interconnections makes the chip area and delay much smaller leading to reduced cross talk noise and improved reliability. Thus, the inclusion of multiple-valued logic in a otherwise mixed design, consisting of analog and binary logic, can make the transition from analog to digital world much more smoother and at the same time improve the overall system performance. As the sizes of integrated devices decrease, maximum voltage ratings also rapidly decrease. Although decreased supply voltages do not restrict the design of digital circuits, it is harder to design high performance analog and multiple valued integrated circuits using new processes. As an alternative to voltage-mode signal processing, current-mode circuit techniques, which use current as a signal carrier, are drawing strong attention today due to their potential application in the design of high-speed mixed-signal processing circuits in low-voltage standard VLSI CMOS technologies. Industrial interest in this field has been propelled by the proposal of innovative ideas for filters, data converters and IC prototypes in the high frequency range [Tou90, Kol00]. Further, in MVL design using conventional CMOS processing, different current levels can be easily used to represent different logic values. Thus the case for an integrated approach to the design of analog, multi-valued and binary logic circuits using current-mode techniques seems to be worth considering. The work presented in this thesis is an effort to reaffirm the utility of current-mode circuit techniques to some of the existing as well as to some new areas of circuit design. We present new algorithms for the synthesis of a class of analog and multiple-valued logic circuits assuming an underlying CMOS current-mode building blocks. Next we present quaternary current-mode signaling scheme employing a simple encoder and decoder architecture for improving the signal delay characteristics of long interconnects in digital logic blocks. As an interface between analog and digital domain, we present an architecture of current-mode flash A/D converter. Finally, low power being a dominant design constraint in today IC technology, we present a scheme for static power minimization in a class of Current-mode circuits.

Orientador: José Alexandre Diniz / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-21T10:50:41Z (GMT). No. of bitstreams: 1 Silva_AudreyRoberto_M.pdf: 3023922 bytes, checksum: ee750f675d01f2b3ceebd5d74149b16e (MD5) Previous issue date: 2012 / Resumo: Este trabalho apresenta o desenvolvimento de células fotovoltaicas de junção n+/p em substratos de Si com processos de fabricação totalmente compatíveis com a tecnologia CMOS (Complementary Metal Oxide Semiconductor). Os processos compatíveis desenvolvidos neste trabalho sao as técnicas: i) de texturização da superfície do Si, com reflexao da superficie texturizada de 15% obtida com a formação de micro-pirâmides (alturas entre 3 e 7 ?m), utilizando-se solução alcalina de NH4OH (hidróxido de amônia), que e livre da contaminação indesejável por íons de Na+ e K+ quando se utiliza soluções tradicionais de NaOH e de KOH, respectivamente, e ii) de deposição ECR-CVD (Electron Cyclotron Resonance - Chemical Vapor Deposition) da camada antirrefletora (ARC) de SiNX (nitreto de silício), que e executada em temperatura ambiente, portanto pode ser feita apos a finalização da célula sem danificar trilhas metálicas e alterar a profundidade da junção n+/p. A caracterização desta camada ARC mostrou que o nitreto tem índice de refração de 1,92 e refletância mínima de 1,03%, o que e um excelente resultado para uso em células solares (ou fotovoltaicas). Foram fabricadas cinco series de células fotovoltaicas, utilizando-se a texturização com NH4OH e a camada antirrefletora de nitreto de Si. Em quatro series utilizou-se o processo de implantação de íons de fósforo (31P+), com posterior recozimento, para a formação da região n+, enquanto que na quinta serie foi utilizado o processo de difusão térmica. As eficiências máximas para as células fabricadas são de 9% e de 12%, respectivamente, para as células feitas utilizando os processos de implantação e de difusão térmica, indicando que a implantação de íons causa danos na rede cristalina do silício, que o posterior recozimento não consegue corrigir, o que reduz a eficiência da célula / Abstract: This work presents the development of photovoltaic cells based on n+/p junction in Si substrates, with fully compatible fabrication processes with CMOS technology. The compatible processes, which are developed in this study, are the techniques: i) of Si surface texturing, with the textured surface reflection of 15% obtained by the formation of micro-pyramids (heights between 3 and 7 ?m) using NH4OH (ammonium hydroxide) alkaline solution, which is free of undesirable contamination by Na + and K + ions, when NaOH and KOH traditional solutions are used, respectively, and ii) of the ECR-CVD (Electron Cyclotron Resonance - Chemical Vapor Deposition) deposition of SiNx (silicon nitride) anti-reflective coating (ARC), which is carried out at room temperature and can be performed after the end of cell fabrication without damage on metallic tracks and without variation of n+/p junction depth. The ARC coating characterization presented that the silicon nitride has a refractive index of 1.92 and a minimum reflectance of 1.03%, which is an excellent result for application in solar (or photovoltaic) cells. Five series of photovoltaic cells were fabricated, using the NH4OH solution texturing and the silicon nitride antireflective coating. In the first four series, phosphorus (31P+) ion implantation process, with subsequent annealing to get the region n+, was used, while, in the fifth series was used the thermal diffusion process. The maximum efficiency values are of 9% and 12%, respectively, for cells, which were fabricated using the ion implantation and thermal diffusion processes, indicating that the ion implantation damages the silicon crystal lattice and the subsequent annealing cannot rectify, which reduces the cell efficiency / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Orientador: Jose Antonio Siqueira Dias / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T10:56:11Z (GMT). No. of bitstreams: 1 Amaral_WellingtonAvelinodo.pdf: 14948298 bytes, checksum: 62522f5a0f70fd9563d5ac2c4c4652e2 (MD5) Previous issue date: 2009 / Resumo: Este trabalho teve como finalidade o projeto e prototipagem de uma referência de tensão CMOS (Complementary Metal Oxide Semiconductor) baseada na tensão de limiar do transistor MOS (Metal Oxide Semiconductor). A inovação apresentada neste trabalho é a utilização de uma arquitetura original e com alto desempenho. Nas medidas realizadas em laboratório o circuito apresentou uma variação de 11ppm/0C. Desempenho este comparável às referências do tipo bandgap. Também foi projetado um sensor de temperatura com coeficiente térmico igual a 1mV/0C. Portanto, dois circuitos foram enviados para fabricação (o circuito ceinv35 e o circuito ceinv66). O circuito ceinv35, utilizando suas estruturas de trimmer, pode operar como referência de tensão ou como sensor de temperatura. O circuito ceinv66 foi a principal configuração estudada. Ele utiliza um circuito extrator de Vth, um circuito de start-up e um amplificador operacional. O circuito extrator de Vth utiliza uma topologia inovadora. Nos dois circuitos (ceinv35 e ceinv66) foram utilizadas estruturas de trimmer para possibilitar ajustes externos. No capítulo de introdução é apresentado um "overview" dos circuitos utilizados como referência de tensão. São analisadas algumas referências do tipo bandgap e algumas técnicas usualmente utilizada para o projeto de referências de tensão CMOS. No capítulo 2 são analisados o princípio de funcionamento e todo o equacionamento do circuito proposto. No capítulo 3 são apresentados os resultados de simulação. O circuito ceinv35 apresentou um coeficiente térmico igual a 1mV/0C, funcionando ele como sensor de temperatura. Já operando como referência de tensão, a variação apresentada foi de 4:06ppm/0C. O circuito ceinv66 apresentou uma variação de apenas 3:14ppm/0C. O capítulo 4 cobre o projeto dos layouts dos circuitos. Eles foram projetados utilizando a tecnologia da AMS (Austria Microsystems) de comprimento mínimo de canal igual a 0:35_m. No capítulo 5 são apresentados os resultados da extração de parasitas dos circuitos. Após esta análise foi verificada a necessidade de reajuste dos circuitos, utilizando as estruturas de trimmer. No capítulo 6 são fornecidos os resultados experimentais dos dois circuitos. No capítulo 7 é apresentada uma alternativa para o projeto da referência de tensão sem a necessidade da utilização do circuito de start-up. Neste mesmo capítulo também é apresentada uma proposta de metodologia para projeto dos trimmers do circuito. No capítulo 8 são discutidas as inovações propostas neste trabalho e algumas conclusões sobre o projeto apresentado. / Abstract: The objective of this work is to design and prototype a CMOS voltage reference based on the threshold voltage of the MOS transistor. The innovation presented in this work is the use of an original architecture with high performance. In the laboratory measurements the circuit presented 11ppm/0C of variation. This performance is comparable to the bandgap references. A temperature sensor was also designed and presented a temperature coefficient of 1mV/0C. Therefore, two circuits were prototyped (the ceinv35 circuit and the ceinv66 circuit). The circuit ceinv35, using the trimmer structures, can operate as a voltage reference or a temperature sensor. The circuit ceinv66 was the main topology studied. It uses a Vth extractor circuit, a start-up circuit and an operational amplifier. The Vth extractor circuit uses an original topology. In both circuits (ceinv35 and ceinv66) were used trimmer structures to make possible off-chip adjusts. In the introduction chapter is presented an overview of the circuits used as voltage references. Some bandgap references and some techniques used to design CMOS voltage references are analyzed. In chapter 2 are shown the operation principles and the equations extracted of the proposed circuit. In chapter 3 are shown the simulation results. The circuit ceinv35 presented a temperature coefficient of 1mV/0C, working as a temperature sensor. On the other side, working as a voltage reference, the variation presented was 4:06ppm/0C. The circuit ceinv66 presented a variation of just 3:14ppm/0C. The chapter 4 covers the layout design of the circuits. The AMS (Austria Microsystems) technology with a minimum channel length of 0:35_m was used. In chapter 5 are presented the parasitic extraction simulations. After this analyses new adjusts were made in the circuits. The trimmers structures were used for this adjusts. In chapter 6 are provided the experimental results of both circuits. In chapter 7 is presented an alternative for the voltage reference design without using a start-up circuit. In this chapter is also presented a methodology for the trimmers design. In chapter 8 are discussed the proposed innovations and some conclusions about the design presented. / Universidade Estadual de Campi / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica