Recently, due to the increasing adoption of distributed energy resource (DER) technologies including battery energy storage (BES) and electric vehicle (EV) systems, bidirectional power converters are becoming more popular. These converters are broadly utilized as interface devices and provide a bidirectional power flow in applications where the primary power supply can both supply and receive energy. A dc capacitor, called the dc-link, is an important component of such bidirectional converters. For a wide range of applications, the converter is required to control the dc-link voltage. Commonly, a proportional-integrating (PI) controller is used by the dc capacitor voltage controller to generate a set-point for the inner current controller. This approach tightly regulates the dc-link voltage to a given value. The research presented in this dissertation shows that such an approach compromises the stability margins of the converter for reverse power flow and weak grid conditions. It is shown that by allowing a small variation of dc capacitor voltage in proportion to the amount of power flowing through the converter, the stability and robustness margins are improved. This approach also simplifies the design process and can be applied to both dc/dc and dc/ac (single-phase and three-phase) converters. Moreover, it grants an inherent power sharing capability when multiple converters share the same dc-link terminals; removing the need to a communication link between parallel converters. The proposed controller is equipped with a current limiting mechanism to protect the converter during low-voltage/over-current transients. Detailed analyses, simulations, comparisons, and experimental results are included to illustrate the effectiveness of the proposed control approach. To mathematically establish the properties of the proposed method in a single-phase dc/ac application, this dissertation also derives a new and systematic modeling approach for a grid-connected bidirectional single-phase inverter controlled in stationary frame. Implementing the control system in the stationary frame has advantages over rotating frame. However, the combination of dc and ac state variables and nonlinearities make its stability analysis challenging. In the proposed model, an imaginary subsystem is properly generated and augmented to allow a full transformation to a synchronous rotating frame. The proposed modeling strategy is modular and has a closed form which facilitates further extensions. It is successfully used to demonstrate enhanced stability margins of the proposed controller.

Digital Switched mode power supplies are nowadays popular enough to be the obvious choice in many applications. Among all set-up and control techniques, the current mode DC-DC converter is often considered when performance and stability are of interest. This has also motivated all the “on chip” and ASIC implementations seen on the market, where current mode control technique is used. However, the development of FPGAs has created an important alternative to ASICs and DSPs. The flexibility and integration possibility is two important advantages among others. In this thesis report, an FPGA-based current mode buck/boost DC-DC converter is built in a stepwise manner, starting from the mathematical model. The goal is a simulation model which creates a basis for discussion about the advantages and disadvantages of current mode DC-DC converters, implemented in FPGAs.

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / For research purposes on helicopter rotor acoustics a large data acquisition system called TEDAS (Transputer based Expandable Data Acquisition System) has been developed. The key features of this system are: unlimited expandability and sum data rate, local storage of data during operation, very simple analog anti aliasing filtering due to extensive digital filtering, and integrated computational power which scales with the number of channels. The sample rate is up to 50 kHz/channel, the resolution is 16 bit, 360 channels are realized now. TEDAS consists of blocks with 8 A/D converters which are controlled by one transputer T800. The size of the local memory is 4 Mbyte. Any number of blocks (IDAM = Intelligent Data Acquisition Module) can be combined to a complete system. Data preprocessing is done in parallel inside the IDAMs. As for 16 bit systems the analog antialiasing filtering becomes a dominant factor of the costs, delta sigma ADCs with oversampling and internal digital filtering are used. This produces an exact linear phase and a stop band rejection of -90 dB.

Tunability and adaptability for radio frequency (RF) front-ends are highly desirable because they not only enhance functionality and performance but also reduce the circuit size and cost. This thesis presents a number of novel design strategies in DC-DC converters, impedance networks and adaptive algorithms for tunable and adaptable RF based mobile telecommunication systems. Specifically, the studies are divided into three major directions: (a) high voltage switch controller based DC-DC converters for RF switch actuation; (b) impedance network designs for impedance transformation of RF switches; and (c) adaptive algorithms for determining the required impedance states at the RF switches. In the first stage, two-phase step-up switched-capacitor (SC) DC-DC converters are explored. The SC converter has a simple control method and a reduced physical volume. The research investigations started with the linear and the non-linear voltage gain topologies. The non-linear voltage gain topology provides a higher voltage gain in a smaller number of stages compared to the linear voltage gain topology. Amongst the non-linear voltage gain topologies, a Fibonacci SC converter has been identified as having lower losses and a higher conversion ratio compared to other topologies. However, the implementation of a high voltage (HV) gain Fibonacci SC converter is complex due to the requirement of widely different gate voltages for the transistors in the Fibonacci converter. Gate driving strategies have been proposed that only require a few auxiliary transistors in order to provide the required boosted voltages for switching the transistors on and off. This technique reduces the design complexity and increases the reliability of the HV Fibonacci SC converter. For the linear voltage gain topology, a high performance complementary-metaloxide- semiconductor (CMOS) based SC DC-DC converter has been proposed in this work. The HV SC DC-DC converter has been designed in low voltage (LV) transistors technology in order to achieve higher voltage gain. Adaptive biasing circuits have been proposed to eliminate the leakage current, hence avoiding latch-up which normally occurs with low voltage transistors when they are used in a high voltage design. Thus, the SC DC-DC converter achieves more than 25% higher boosted voltage compared to converters that use HV transistors. The proposed design provides a 40% power reduction through the charge recycling circuit that reduces the effect of non-ideality in integrated HV capacitors. Moreover, the SC DC-DC converter achieves a 45% smaller area than the conventional converter through optimising the design parameters. In the second stage, the impedance network designs for transforming the impedance of RF switches to the maximum achievable impedance tuning region are investigated. The maximum achievable tuning region is bounded by the fundamental properties of the selected impedance network topology and by the tunable values of the RF switches that are variable over a limited range. A novel design technique has been proposed in order to achieve the maximum impedance tuning region, through identifying the optimum electrical distance between the RF switches at the impedance network. By varying the electrical distance between the RF switches, high impedance tuning regions are achieved across multi frequency standards. This technique reduces the cost and the insertion loss of an impedance network as the required number of RF switches is reduced. The prototype demonstrates high impedance coverages at LTE (700MHz), GSM (900MHz) and GPS (1575MHz). Integration of a tunable impedance network with an antenna for frequency-agility at the RF front-end has also been discussed in this work. The integrated system enlarges the bandwidth of a patch antenna by four times the original bandwidth and also improves the antenna return loss. The prototype achieves frequency-agility from 700MHz to 3GHz. This work demonstrates that a single transceiver with multi frequency standards can be realised by using a tunable impedance network. In the final stage, improvement to an adaptive algorithm for determining the impedance states at the RF switches has been proposed. The work has resulted in one more novel design techniques which reduce the search time in the algorithm, thus minimising the risk of data loss during the impedance tuning process. The approach reduces the search time by more than an order of magnitude by exploiting the relationships among the mass spring’s coefficient values derived from the impedance network parameters, thereby significantly reducing the convergence time of the algorithm. The algorithm with the proposed technique converges in less than half of the computational time compared to the conventional approach, hence significantly improving the search time of the algorithm. The design strategies proposed in this work contribute towards the realisation of tunable and adaptable RF based mobile telecommunication systems.

International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California / During high-power microwave (HPM) testing, where the item under test is subjected to power levels up to several thousand W/cm , the RF energy present will make typical 2 telemetry RF links useless. Therefore, other means must be used to retrieve the data during the tests. One method to accomplish data retrieval is to replace the RF data link with a fiber-optic link. This is done by replacing the transmitter with a fiber-optic transmitter on the sending end and the RF receiver with a fiber-optic receiver on the receiving end. Although this sounds simple, it is not always so. Solutions for PCM and FM-FM systems are relatively straightforward, whereas PAM systems present a unique set of problems. This paper addresses possible solutions for PCM and FM-FM and three possible solutions for PAM, one being by using a PAM-to-PCM converter.

In this project, the wave energy converter (WEC) designed at Seabased AB and Uppsala University was modelled in the program MATLAB. In order to increase the average output power, the WEC should be controlled. Therefore, the simulation tool was used to investigate damping strategies where the damping coefficient was changed at different times of the wave period. The tests showed that a suitable damping strategy, matched to the sea state at the specific location of the site and the overall WEC design, increases the average output power, as well as may protect the WEC from damages. This can lead to a more sustainable WEC system, which may contribute to the increasing demand of renewable energy solutions.

This document explores the isolated multiple-input single ended primary inductor converter (IMISEPIC) and discusses its application. This thesis proposes the following control methods such as current feed-forward control, voltage feedback control and maximum power point control to analyze the IMISEPIC. Zero-ripple technique is also applied to IMISEPIC in order to increase the converter’s life-time. Design strategy and concerns about the IMISEPIC are also presented, and simulations and circuit experiments are conducted to verify the analysis. Finally, the discussion about control limitation is used for future design consideration. / text

This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

A novel, variable-gain switched-capacitor DC-DC converter is designed, constructed and tested. The proposed converter minimizes many of the problems which have traditionally hindered switched-capacitor DC-DC converters. The converter has high efficiency, strong regulation and low output voltage ripple across a wide variation in the line and load. The converter utilizes an optimized switching configuration that contains the maximum number of ideal conversion ratios for the given number of capacitors driven by a two-phase clock. The switched-capacitor converter is controlled by a gain-hopping feedforward control scheme in conjunction with duty-cycle, pulse-width modulation feedback control. The proposed control technique enhances the efficiency and regulation capability of switched-capacitor DC-DC converters, which are typically limited when there is a large variation in the line. Because the converter is optimized, programmable and capable of providing buck and/or boost operation (stepping-up and/or stepping-down the input voltage), the new switched-capacitor DC-DC converter is well-suited for a variety of applications and operating conditions. In addition, a novel algorithm based on graph theory and network analysis is developed which enumerates all possible ideal conversion ratios for a given switched-capacitor DC-DC converter structure. In particular, this algorithm can be used as a design tool to greatly improve the operation of multi-gain switched-capacitor converters, where the aim is to maximize the number of ideal conversion ratios while minimizing the number of switches and capacitors. Furthermore, the structure of all attainable positive, ideal conversion ratios of a two-phase switched-capacitor DC-DC converter, utilizing up to five capacitors, is enumerated. As a result, the design process for switched-capacitor converters is greatly simplified and a suitable converter structure can be more easily selected for a given application. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2013-04-03 23:27:24.183

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / Chart recorders currently in use on telemetry ranges are connected to telemetry processors via a series of Digital to Analog Converters (DAC) systems. A new modular interface system receives data directly from the processor broadcast bus and distributes them to up to ten digital chart recorders. This interface is programmed from a computer to assign individual tags to each one of the display channels. This system eliminates DAC's and patch panels. It simplifies display system operation, speeds up transition from test to test and reduces maintenance costs.