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The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.

This theses analyzes Cuk converter, that is one of the dc to dc switching converters. For continuous inductor current mode and discontinuous inductor current mode, stedy state operation is analysied. Characteristic parameters are determined. Through State Space Averge Models, Small Signal Models are obtained. Parasitic Resistance effects on steady state and small signal models are determined. Efficency of the switching converter is derived. Open loop transfer functions for continous and discontinuous inductor curret mode are obtained. Parmeters for small signal behaviour is determined and stability is analysied. Parasitic resistance effects on transfer functions is determined. Therotecial analysis are verified with a simulations of designed converter.

The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. Rapid progress in silicon VLSI technologies has made it possible to implement multi-function and high performance electronic circuits on a single die. Coupled with this, the need for interfacing digital blocks to the external world resulted in the integration of analog blocks such as A/D and D/A converters, filters and oscillators with the digital logic on the same die. Thus, mixed signal system-on-chip (SOC) solutions are becoming a common practice in the present day integrated circuit (IC) technologies. In digital domain, aggressive technology scaling redefines, in many ways, the role of interconnects vis-`a-vis the logic in determining the overall performance. Apart from signal integrity, power dissipation and reliability issues, delays over long interconnects far exceeding the logic delay becomes a bottleneck in high speed operation. Moreover, with an increasing density of chips, the number of interchip connections is greatly increased as more and more functions are put on the same chip; thus, the size and performance of the chip are mostly dominated by wiring rather than devices. One of the most promising approaches to solve the above interconnection problems is the use of multiple-valued logic (MVL) inside the chip [Han93, Smi88]. The number of interconnections can be directly reduced with multiple valued signal representation. The reduced complexity of interconnections makes the chip area and delay much smaller leading to reduced cross talk noise and improved reliability. Thus, the inclusion of multiple-valued logic in a otherwise mixed design, consisting of analog and binary logic, can make the transition from analog to digital world much more smoother and at the same time improve the overall system performance. As the sizes of integrated devices decrease, maximum voltage ratings also rapidly decrease. Although decreased supply voltages do not restrict the design of digital circuits, it is harder to design high performance analog and multiple valued integrated circuits using new processes. As an alternative to voltage-mode signal processing, current-mode circuit techniques, which use current as a signal carrier, are drawing strong attention today due to their potential application in the design of high-speed mixed-signal processing circuits in low-voltage standard VLSI CMOS technologies. Industrial interest in this field has been propelled by the proposal of innovative ideas for filters, data converters and IC prototypes in the high frequency range [Tou90, Kol00]. Further, in MVL design using conventional CMOS processing, different current levels can be easily used to represent different logic values. Thus the case for an integrated approach to the design of analog, multi-valued and binary logic circuits using current-mode techniques seems to be worth considering. The work presented in this thesis is an effort to reaffirm the utility of current-mode circuit techniques to some of the existing as well as to some new areas of circuit design. We present new algorithms for the synthesis of a class of analog and multiple-valued logic circuits assuming an underlying CMOS current-mode building blocks. Next we present quaternary current-mode signaling scheme employing a simple encoder and decoder architecture for improving the signal delay characteristics of long interconnects in digital logic blocks. As an interface between analog and digital domain, we present an architecture of current-mode flash A/D converter. Finally, low power being a dominant design constraint in today IC technology, we present a scheme for static power minimization in a class of Current-mode circuits.

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"In this thesis, based on the existing researches on power factor correction technology, I analyze, design and study the Boost type power factor correction technology, which is applied in the in-board two-stage battery charger. First I analyzed the basic working principle of the active power factor corrector. By comparing several different topologies of PFC converter main circuit and control methods, I specified the research object to be the average current control (ACM) boost power factor corrector. Then I calculated and designed the PFC circuit and the ACM controller applied in the first level charging of EVs. And I run the design in Simulink and study the important features like power factor, the input current waveform and the output DC voltage and the THD and odd harmonic magnitude."

Distributed generation is expected to play a significant role in remedying the many shortcomings in today’s energy market. In particular, fuel cell power generation will play a big part due to several advantages. Still, it is faced with its own challenges to tap into its potential as a solution to the crisis. The responsibilities of the Power Conditioning Unit (PCU), and thus its design, are therefore complex, yet critical to the fuel cell system’s performance and ability to meet the requirements. To this end, the dc-dc converter, considered the most critical component of the PCU for optimum performance, is closely examined. The selected converter is first modeled to gain insight into its behavior for the purpose of designing suitable compensators. MATLAB is then used to study the results using the frequency domain, and it was observed that the converter offers its own unique challenges in terms of closed-loop performance and stability. These limitations must therefore be carefully accounted for and compensated against when designing the control loops to achieve the desired objectives. Negative feedback control to ensure robustness is then discussed. The insertion of a second inner loop in Current Mode Control (CMC) offers several key advantages over single-loop Voltage Mode Control (VMC). Furthermore, the insertion of a Current Error Amplifier (CEA) in Average Current Mode Control (ACMC) helps overcome many of the problems present in Peak Current Mode Control (PCMC) whilst allowing much needed design flexibility. It is therefore well suited for this application in an attempt to improve the dynamic behavior and overcoming the shortcomings inherent in the converter. The modulator and controller for ACMC are then modeled separately and combined with the converter’s model previously derived to form the complete small-signal model. A suitable compensation network is selected based on the models and corresponding Bode plots used to assess the system’s performance and stability. The resulting Bode plot for the complete system verifies that the design objectives are clearly met. The complete system was also built in MATLAB/Simulink, and subjected to external disturbances in the form of stepped load changes. The results confirm the system’s excellent behavior despite the disturbance, and the effectiveness of the control strategy in conjunction with the derived models. To meet the demand in many applications for power sources with high energy density and high power density, it is constructive to combine the fuel cell with an Energy Storage System (ESS). The hybrid system results in a synergistic system that brings about numerous potential advantages. Nevertheless, in order to reap these potential benefits and avoid detrimental effects to the components, a suitable configuration and control strategy to regulate the power flow amongst the various sources is of utmost importance. A robust and flexible control strategy that allows direct implementation of the ACMC scheme is devised. The excellent performance and versatility of the proposed system and control strategy are once again verified using simulations. Finally, experimental tests are also conducted to validate the results presented in the dissertation. A scalable and modular test station is built that allows an efficient and effective design and testing process of the research. The results show good correspondence and performance of the models and control design derived throughout the thesis.

Distributed generation is expected to play a significant role in remedying the many shortcomings in today’s energy market. In particular, fuel cell power generation will play a big part due to several advantages. Still, it is faced with its own challenges to tap into its potential as a solution to the crisis. The responsibilities of the Power Conditioning Unit (PCU), and thus its design, are therefore complex, yet critical to the fuel cell system’s performance and ability to meet the requirements. To this end, the dc-dc converter, considered the most critical component of the PCU for optimum performance, is closely examined. The selected converter is first modeled to gain insight into its behavior for the purpose of designing suitable compensators. MATLAB is then used to study the results using the frequency domain, and it was observed that the converter offers its own unique challenges in terms of closed-loop performance and stability. These limitations must therefore be carefully accounted for and compensated against when designing the control loops to achieve the desired objectives. Negative feedback control to ensure robustness is then discussed. The insertion of a second inner loop in Current Mode Control (CMC) offers several key advantages over single-loop Voltage Mode Control (VMC). Furthermore, the insertion of a Current Error Amplifier (CEA) in Average Current Mode Control (ACMC) helps overcome many of the problems present in Peak Current Mode Control (PCMC) whilst allowing much needed design flexibility. It is therefore well suited for this application in an attempt to improve the dynamic behavior and overcoming the shortcomings inherent in the converter. The modulator and controller for ACMC are then modeled separately and combined with the converter’s model previously derived to form the complete small-signal model. A suitable compensation network is selected based on the models and corresponding Bode plots used to assess the system’s performance and stability. The resulting Bode plot for the complete system verifies that the design objectives are clearly met. The complete system was also built in MATLAB/Simulink, and subjected to external disturbances in the form of stepped load changes. The results confirm the system’s excellent behavior despite the disturbance, and the effectiveness of the control strategy in conjunction with the derived models. To meet the demand in many applications for power sources with high energy density and high power density, it is constructive to combine the fuel cell with an Energy Storage System (ESS). The hybrid system results in a synergistic system that brings about numerous potential advantages. Nevertheless, in order to reap these potential benefits and avoid detrimental effects to the components, a suitable configuration and control strategy to regulate the power flow amongst the various sources is of utmost importance. A robust and flexible control strategy that allows direct implementation of the ACMC scheme is devised. The excellent performance and versatility of the proposed system and control strategy are once again verified using simulations. Finally, experimental tests are also conducted to validate the results presented in the dissertation. A scalable and modular test station is built that allows an efficient and effective design and testing process of the research. The results show good correspondence and performance of the models and control design derived throughout the thesis.

Ultra-low-power circuits are becoming more desirable due to growing portable device markets and they are also becoming more interesting and applicable today in biomedical, pharmacy and sensor networking applications because of the nano-metric scaling and CMOS reliability improvements. In this thesis, three main achievements are presented in ultra-low-power adders. First, a new majority function algorithm for carry and the sum generation is presented. Then with this algorithm and implied new architecture, we achieved a circuit with 75mV supply voltage operation. Last but not least, a 64 bit current-mode majority-function adder based on the new architecture and algorithm is successfully tested at 75mV supply voltage. The circuit consumed 4.5nW or 3.8pJ in one of the worst conditions.

The summing amplifier and the quantizer form two of the most critical blocks in a continuous time delta sigma (CT ΔΣ) analog-to-digital converter (ADC). Most of the conventional CT ΔΣ ADC designs incorporate a voltage summing amplifier and a voltage-mode quantizer. The high gain-bandwidth (GBW) requirement of the voltage summing amplifier increases the overall power consumption of the CT ΔΣ ADC. In this work, a novel method of performing the operations of summing and quantization is proposed. A current-mode summing stage is proposed in the place of a voltage summing amplifier. The summed signal, which is available in current domain, is then quantized with a 3-bit current mode flash ADC. This current mode summing approach offers considerable power reduction of about 80% compared to conventional solutions [2]. The total static power consumption of the summing stage and the quantizer is 5.3mW. The circuits were designed in IBM 90nm process. The static and dynamic characteristics of the quantizer are analyzed. The impact of process and temperature variation and mismatch tolerance as well as the impact of jitter, in the presence of an out-of-band blocker signal, on the performance of the quantizer is also studied.