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Ce mémoire fait tout d’abord l’état de l’art des filtres reconfigurables (passifs et actifs) pour les radiocommunications. Les différentes architectures de réception sont comparées pour déterminer celles qui sont les mieux adaptées aux récepteurs de type multistandard. Les concepts de radio logicielle et de radio cognitive ainsi que la façon de les mettre en œuvre sont ensuite indiqués afin de souligner l’intérêt d’utiliser des filtres reconfigurables. Les notions de filtres réglables, reconfigurables et agiles qui sont alors comparées illustrent tout l’intérêt des filtres agiles. Une nouvelle théorie qui permet pour la première fois la réalisation de filtres passe bande du second ordre entièrement actifs à fréquence agile est ensuite introduite. Un amplificateur de contre réaction dont le gain est réglable permet de modifier facilement la valeur de la fréquence centrale du filtre obtenu. Cette théorie est ensuite généralisée et ses nouvelles propriétés sont étudiées. Il en résulte alors une plage de réglage de la fréquence beaucoup plus étendue. Des filtres passe bande ont été réalisés en mode courant en technologie SiGe BiCMOS 0.25 µm de STMicroelectroincs à partir de convoyeurs de courant contrôlés (CCCII). Les résultats de simulation obtenus pour ces différents filtres confirment les avantages de cette théorie. Ils montrent ainsi que la généralisation précédente conduit à des structures entièrement actives dont la plage de réglage de la fréquence augmente et la puissance dissipée diminue. Des résultats de mesure obtenus sous pointes pour un filtre passe bande réalisé dans la technologie précédente sont donnés. Ils sont aussi en parfait accord avec cette théorie. Cette nouvelle approche permettra de réaliser des filtres agiles pour les récepteurs multistandard de radiocommunication. / In this thesis, we explore the state of the art of reconfigurable filters (passive and active) used in radio-communications. Different receiving architectures are compared to determine the most suitable for multi-standard devices. The concept of software and cognitive radio as well as the means to implement them are indicated in order to highlight the advantage of reconfigurable filters. The concepts of tunable, reconfigurable and agile filters are compared, illustrating the advantage agile ones. A new theory which allows, for the first time, the realization of second order band-pass fully active filters is then introduced. A feedback amplifier with tunable gain allows modifying easily the center frequency of the resulting filter; this theory is then generalized and its new properties are studied. This results in a large frequency tuning range. Current mode band-pass filters are implemented in SiGe BiCMOS 0.25 µm from STMicroelectroincs using current controlled conveyors (CCCII), the simulation results confirm the interest of this theory. They also show that the generalization leads to entirely active structures whose tuning range increases while its power dissipation decreases. The measurements carried out on the fabricated chip are given; they are in perfect agreement with this theory. The new approach allows realizing agile filters for multi-standard radio-communication receivers.

Este trabalho propõe uma metodologia de projeto para células digitais MOS Current-Mode Logic (MCML) e faz um estudo da utilização destes circuitos, frente à utilização de células CMOS tradicionais. MCML é um estilo lógico desenvolvido para ser utilizado em circuitos de alta frequência e tem como princípio de funcionamento o direcionamento de uma corrente de polarização através de uma rede diferencial. Na metodologia proposta o dimensionamento inicial da célula lógica é obtido a partir do modelo quadrático de transistores e através de simulações SPICE analisa-se o comportamento da célula e se redimensiona a mesma para obter as especificações desejadas. Esta metodologia considera que todos os pares diferencias da rede de pull-down possuem o mesmo dimensionamento. O objetivo através desta metodologia é encontrar a melhor frequência de operação para uma dada robustez da célula digital. Dimensionamos células lógicas MCML de até três entradas para três tecnologias (XFAB XC06, IBM130 e PTM45). Comparamos os resultados da metodologia proposta com o software comercial de otimização de circuitos, Wicked™, o qual obteve uma resposta de atraso 20% melhor no caso da tecnologia XFAB XC06 e 3% no caso do processo IBM130. Através de simulações de osciladores em anel, demonstramos que a topologia MCML apresenta vantagens sobre as células digitais CMOS estáticas, em relação à dissipação de potência quando utilizada em circuitos de alta frequência e caminhos de baixa profundidade lógica. Também demonstramos, através de divisores de frequência, que estes circuitos quando feitos na topologia MCML podem atingir frequências de operação que em geral são o dobro das apresentadas em circuitos CMOS, além do mais atingem este desempenho com uma dissipação de potência menor que circuitos CMOS. A natureza analógica das células MCML as torna susceptíveis às variações de processo. Variações globais são compensadas pelo aumento dos transistores da PDN, já casos de descasamentos, por não terem um método de compensação, acabam por degradar a confiabilidade do circuito. Na avaliação da área ocupada por célula, a topologia MCML mostrou consumir mais área do que a topologia CMOS. / This work proposes a simulation-based methodology to design MOS Current-Mode Logic (MCML) gates and addresses the tradeoffs of the MCML versus static CMOS circuits. MCML is a design style developed focusing in a high-speed logic circuit. This logic style works with the principle of steering a constant bias current through a fully differential network of input transistors. The proposed methodology uses the quadratic transistor model to find the first design solution, through SPICE simulations, make decisions and resizes the gate to obtain the required solution. The method considers a uniform sizing of the pull-down network transistors. The target solution is the best propagation delay for a predefined gate noise margin. We design MCML gates for three different process technologies (XFAB XC06, IBM130 and PTM45), considering gates up to three inputs. We compare the solutions of the proposed methodology against commercial optimization software, Wicked™, that considers different sizing for PDN differential pairs. The solutions of the software results in a 20% of improvement, when compared to the proposed methodology, in the worst case input delay for the XFAB XC06 technology, and 3% in IBM130. We demonstrate through ring oscillators simulations that MCML gates are better for high speed and small logic path circuits when compared to the CMOS static gates. Moreover, by using MCML frequency dividers we obtained a maximum working frequency that almost doubles the frequency achieved by CMOS frequency dividers, dissipating less power than static CMOS circuits. We demonstrate through a reliability analysis that the analog behavior of MCML gates makes them susceptible to PVT variations. The global variations are compensated by the bias control circuits and with the increase of the PDN transistor width. This procedure compensates the gain loss of these transistors in a worst case variation. In other hand, this increasing degrades the propagation delay of the gates. The MCML gates reliability is heavily affected by the mismatching effects. The difference of the mirrored bias current and the mismatching of the differential pairs and the PUN degrade the design yield. The results of the layout extracted simulations demonstrate that MCML gates performs a better propagation delay performance over gates that depend on complexes pull-up networks in standard CMOS implementation, as well as multi-stages static CMOS gates. Considering the gate layout implementation we demonstrate that the standard structures of pull-up and bias current mirror present in the gate are prejudicial for the MCML gate area.

The main goal of this thesis is to develop an active thermal management control scheme for multi-phase current mode buck converters in order to improve the long term reliability of the converters. A thermal management unit (TMU) with independent linear compensators for the thermal loops is incorporated into the existing digital controller to regulate the current through each phase so that equal temperature distribution is achieved across all phases. A lumped parameter thermal model of the multi-phase converter is built as the basis of the TMU. MATLAB simulation results are used to verify the TMU concept. Experimental results from a digitally controlled 12 V to 1 V, 50 A, 250 kHz four-phase peak current mode buck converter demonstrate the effectiveness of the proposed thermal management technique in the presence of uneven air flow. The steady-state performance, dynamic transient load performance, effect of gate drive voltage and efficiency measurements are investigated and discussed.

The main goal of this thesis is to develop an active thermal management control scheme for multi-phase current mode buck converters in order to improve the long term reliability of the converters. A thermal management unit (TMU) with independent linear compensators for the thermal loops is incorporated into the existing digital controller to regulate the current through each phase so that equal temperature distribution is achieved across all phases. A lumped parameter thermal model of the multi-phase converter is built as the basis of the TMU. MATLAB simulation results are used to verify the TMU concept. Experimental results from a digitally controlled 12 V to 1 V, 50 A, 250 kHz four-phase peak current mode buck converter demonstrate the effectiveness of the proposed thermal management technique in the presence of uneven air flow. The steady-state performance, dynamic transient load performance, effect of gate drive voltage and efficiency measurements are investigated and discussed.

As the volume of data processed by computers and telecommunication devices rapidly increases, high speed serial link has been challenged to maximize its I/O bandwidth with limited resources of channels and semiconductor devices. This trend requires designers’ relentless effort for innovations. The innovations are required not only at system level but also at sub-system and circuit level. This dissertation discusses two important topics regarding high speed serial links: Clock and Data Recovery (CDR) and Current Mode Logic (CML). This dissertation proposes a mixed-mode adaptive loop gain Bang-Bang CDR. The proposed CDR enhances jitter performances even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of the Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode-based Charge Pump (CP) is proposed to minimize CP latency. The effectiveness of the proposed techniques was experimentally demonstrated by various jitter performance tests. This dissertation also presents a process-variation-resilient CML. A typical CML requires over-design to meet the specification over the wide range of process parameter variations. To address this issue, the proposed CML employs a time-reference-based adaptive biasing chain with replica load. It adjusts a variable load resistor to simultaneously regulate time-constant, voltage swing, level-shifting and DC gain. The performance of the high speed building blocks such as Bang-Bang Phase Detectors, frequency dividers and PRBS generators can be more accurately regulated with the proposed CML approach. The prototype is fabricated to experimentally compare the process-variation-induced performance degradation between the conventional and the proposed CML. Compared to the conventional CML, the proposed architecture significantly reduces the performance degradation on divider self-oscillation frequency, PRBS generator speed and PRBS output jitters over the process-variation with only <3% additional power dissipation.

Power management components can be found in a host of different applications ranging from portable hand held gadgets to modern avionics to advanced medical instrumentations, among many other applications. Low-dropout (LDO) linear regulators are particularly popular owing to their: ease of use, low cost, high accuracy, low noise, and high bandwidth. With all its glory, however, it tends to underperform switched-mode power supplies (SMPS) when with comes to power conversion efficiency, although the later generates a lot of ripple at its output. With the growing need to improve system efficiency (hence longer battery life) without degrading system performance, many high end (noise sensitive) applications such as data converters, RF transceivers, precision signal conditioning, among others, use high efficiency SMPS with LDO regulators as post-regulators for rejecting the ripple generated by SMPS. This attribute of LDO regulators is known as power supply rejection (PSR). With the trend towards increasing switching frequency for SMPS, to minimize PC board real estate, it is becoming ever more difficult for LDO regulators to suppress the associate high frequency ripple since at such high frequencies, different parasitic components of the LDO regulator start to deteriorate its PSR performance. There have been a handful of different techniques suggested in the literature that can be used to achieve good PSR performance at higher frequencies. However, each of these techniques suffers from a number of drawbacks ranging from reduced efficiency to increased cost to increased solution size, and with the growing demand for higher efficiency and smaller power supplies, these techniques have their clear limitations. The objective of this research project is to develop a novel current-mode LDO regulator that can achieve good high frequency PSR performance without suffering from the afore mentioned drawbacks. The proposed architecture was fabricated using a proprietary 1.5 um Bipolar process technology, and the measurement results show a PSR improvement of 20dB (at high frequencies) over conventional regulators. Moreover, the proposed LDO regulator requires a small 15nF output capacitor for stability, which is far smaller than some of the currently used techniques.

Τα αναλογικά φίλτρα συνεχούς χρόνου αποτελούν απαραίτητα μέρη ακόμη και στις πιο μοντέρνες ηλεκτρονικές συσκευές, οι οποίες λειτουργούν, κατά το μεγαλύτερο τμήμα τους ψηφιακά. Η εξήγηση είναι απλή, αν αναλογιστεί κανείς πρώτον, ότι, αποτελούν τις ενδιάμεσες βαθμίδες μεταξύ του φυσικού κόσμου και τις –κατά τα άλλα ψηφιακές– συσκευές και δεύτερον ότι, μπορούν να λειτουργήσουν σε υψηλές συχνότητες, όπου τα ψηφιακά κυκλώματα δεν μπορούν. Η προσπάθεια για όλο και πιο βελτιωμένα κυκλώματα, κάνει τους σχεδιαστές ηλεκτρονικών κυκλωμάτων να ψάχνουν για νέες μεθόδους σχεδίασης. Μία από αυτές είναι η σχεδίαση με χρήση τεχνικών τρόπου ρεύματος (current mode), χρήση της οποίας γίνεται στην παρούσα διδακτορική διατριβή. Είναι γνωστό ότι, έως και πριν από μερικά χρόνια, η σχεδίαση κυκλωμάτων γινόταν, σχεδόν αποκλειστικά, για λειτουργία σε τρόπο τάσης. Αυτό σημαίνει ότι, για τα κυκλώματα αυτά, οι ηλεκτρικές μεταβλητές εισόδου και εξόδου είναι τάσεις αφού, η είσοδος των χρησιμοποιούμενων ηλεκτρονικών βαθμίδων είναι υψηλής εμπέδησης ενώ η έξοδός τους χαμηλής. Τα κυκλώματα τρόπου τάσης σχεδιάζονται, ώστε, να λειτουργούν σε αυτές τις στάθμες εμπέδησης, παρά το γεγονός ότι, τα στοιχειώδη ηλεκτρονικά στοιχεία, τα τρανζίστορ, συμπεριφέρονται ως ελεγχόμενες πηγές ρεύματος. Αυτό ακριβώς το γεγονός εκμεταλλεύονται τα κυκλώματα τρόπου ρεύματος, τα οποία, λόγω του ότι εμφανίζουν χαμηλή εμπέδηση εισόδου και υψηλή εμπέδηση εξόδου, επεξεργάζονται ρεύματα απλοποιώντας ταυτόχρονα τον τρόπο σχεδίασης. Για να είναι πραγματικά εφικτή η σχεδίαση για τα κυκλώματα τρόπου ρεύματος είναι απαραίτητο ένα τουλάχιστον ενεργό δομικό στοιχείο. Στην παρούσα διατριβή ως δομικό στοιχείο μελετάται, καταρχήν, ο απλός ενισχυτής ρεύματος. Ο ενισχυτής αυτός αποτελεί τη βάση του διαφορικού ενισχυτή ρεύματος, που με τη σειρά του αποτελεί ένα νέο δομικό στοιχείο πολύ πιο ευέλικτο για ανάπτυξη νέων κυκλωμάτων αναλογικής επεξεργασίας σήματος. Προκύπτει ότι, ο διαφορικός ενισχυτής ρεύματος, ο οποίος λειτουργεί συνήθως, έχοντας ενίσχυση ρεύματος ίση ή λίγο μεγαλύτερη από τη μονάδα, μπορεί να δώσει κυκλώματα, που λειτουργούν σε υψηλότερες συχνότητες συγκριτικά με τα κυκλώματα τρόπου τάσης. Αρκετά κυκλώματα μπορούν να σχεδιαστούν με βάση, είτε τον απλό, είτε το διαφορικό ενισχυτή ρεύματος. Με τη βοήθειά των δύο αυτών στοιχείων αναπτύσσεται ένα πλήθος από βασικά κυκλώματα αναλογικής επεξεργασίας σήματος, όπως εξομοιωμένοι επαγωγοί, ολοκληρωτές, ταλαντωτές καθώς και ενεργά φίλτρα. Στη διατριβή αυτή, αναπτύσσεται, καταρχήν, η σχεδίαση διαφόρων βασικών αναλογικών δομικών βαθμίδων και ακολούθως, παρουσιάζονται οι τεχνικές για τη σχεδίαση ενεργών φίλτρων, ακολουθώντας δύο βασικές μεθόδους, όπως η μέθοδος διασύνδεσης βαθμίδων δεύτερης τάξης και η μέθοδος συναρτησιακής και τοπολογικής εξομοίωσης LC παθητικών κυκλωμάτων. Η μέθοδος της τοπολογικής εξομοίωσης κυκλωμάτων είναι αρκετά ελκυστική, λόγω των δυνατοτήτων, που προσφέρει. Είναι αρκετά εύκολη κατά το σχεδιασμό, τόσο τον ηλεκτρονικό όσο και τον φυσικό (layout), καθώς χρησιμοποιεί επαναλαμβανόμενες δομές. Δύο από τις τεχνικές, που ανήκουν στην κατηγορία της τοπολογικής εξομοίωσης κυκλωμάτων και αναπτύσσονται εδώ, είναι η σχεδίαση κυκλωμάτων με τεχνική τύπου "leapfrog" και η κυματική τεχνική. Με βάση τον διαφορικό ενισχυτή ρεύματος αναπτύσσεται ο τελεστικός ενισχυτής ρεύματος. Το στοιχείο αυτό είναι χρήσιμο σε εφαρμογές, όπου απαιτείται υψηλή ενίσχυση ρεύματος. Η ενίσχυση μπορεί να είναι μεταβαλλόμενη και εξαρτώμενη από μία τάση πόλωσης και αυτό κάνει τον τελεστικό ενισχυτή ρεύματος ένα αρκετά χρήσιμο στοιχείο στην ανάπτυξη εφαρμογών. Η ανάπτυξη ενός τελεστικού ενισχυτή ρεύματος παρουσιάζεται στο τέλος της διατριβής. Όλα τα κυκλώματα, που προτείνονται στην παρούσα διατριβή, είναι ολοκληρώσιμα σε οποιαδήποτε κοινή τεχνολογία ολοκλήρωσης. Ωστόσο, τα προτεινόμενα κυκλώματα σχεδιάζονται για CMOS τεχνολογία, επειδή είναι εξαιρετικά διαδεδομένη και κατάλληλη για τις περισσότερες εφαρμογές αναλογικής επεξεργασίας σήματος. Επιπλέον, τα CMOS κυκλώματα μπορούν σχετικά εύκολα να μετατραπούν σε διπολική ή και BiCMOS τεχνολογία, αφού τοπολογικά διατηρούν την ίδια περίπου δομή. / Continuous-time analog filters are essential parts even of the most modern electronic systems, which in their main part operate digitally. We can explain this by thinking, first, that analog circuits are usually used as necessary intermediate stages between the natural world signals and the electronic digital systems and second, that they are more suitable for operation at high frequencies compared to digital circuits. The designers of electronic circuits in their effort to improve circuits investigate for new design methods. Such a recent method is the so called "current-mode method". Current-mode circuits suitable, mainly for filtering applications, are studied in this thesis. It is known that until recently electronic circuits were considered as circuits operating in voltage-mode. This means that the electric variables for these circuits were taken mainly as voltages in spite of the fact that the elementary electronic devices, that is the transistors, behave as controlled current sources. On the contrary, current-mode circuits take advantage of the real nature of the transistors and thus process currents instead of voltages. This way, the circuit design procedure is significantly simplified, the derived current-mode circuits are much simpler in their structure and in addition, they show better performance at high frequencies. A structural active element is always necessary in every active filter either in the voltage or in the current-mode domain. In this thesis, a single input current amplifier is studied, as such structural active element. This amplifier is used as a subcircuit for obtaining the differential current amplifier, which, accordingly, is used as a new basic active device for the development of new analog signal processing circuits. It is found that the differential current amplifier, which usually operates having low current gain, is suitable for operation at high frequencies comparable to the fT of the transistors used in the amplifier. It is shown that various circuits of general purpose can be obtained, based on a single or a differential current amplifier. In addition, a number of new analog circuits suitable for signal processing are proposed in this thesis. Among them, there are lossy and lossless integrators, simulated inductors, and oscillators. However, emphasis is given to the development of integrated active filters of high order by following various design methods. As a result, the method of the topological simulation of passive LC filter prototypes appears to be more attractive for obtaining high order filters, due to the many possibilities that this method offers. All the proposed circuits in this thesis are suitable for integration in CMOS technology, which is more suitable for analog signal processing applications. Simulation and experimental results taken from implemented integrated circuits verify the accuracy of operation of the proposed circuits and their suitability for practical applications.

Este trabalho propõe uma metodologia de projeto para células digitais MOS Current-Mode Logic (MCML) e faz um estudo da utilização destes circuitos, frente à utilização de células CMOS tradicionais. MCML é um estilo lógico desenvolvido para ser utilizado em circuitos de alta frequência e tem como princípio de funcionamento o direcionamento de uma corrente de polarização através de uma rede diferencial. Na metodologia proposta o dimensionamento inicial da célula lógica é obtido a partir do modelo quadrático de transistores e através de simulações SPICE analisa-se o comportamento da célula e se redimensiona a mesma para obter as especificações desejadas. Esta metodologia considera que todos os pares diferencias da rede de pull-down possuem o mesmo dimensionamento. O objetivo através desta metodologia é encontrar a melhor frequência de operação para uma dada robustez da célula digital. Dimensionamos células lógicas MCML de até três entradas para três tecnologias (XFAB XC06, IBM130 e PTM45). Comparamos os resultados da metodologia proposta com o software comercial de otimização de circuitos, Wicked™, o qual obteve uma resposta de atraso 20% melhor no caso da tecnologia XFAB XC06 e 3% no caso do processo IBM130. Através de simulações de osciladores em anel, demonstramos que a topologia MCML apresenta vantagens sobre as células digitais CMOS estáticas, em relação à dissipação de potência quando utilizada em circuitos de alta frequência e caminhos de baixa profundidade lógica. Também demonstramos, através de divisores de frequência, que estes circuitos quando feitos na topologia MCML podem atingir frequências de operação que em geral são o dobro das apresentadas em circuitos CMOS, além do mais atingem este desempenho com uma dissipação de potência menor que circuitos CMOS. A natureza analógica das células MCML as torna susceptíveis às variações de processo. Variações globais são compensadas pelo aumento dos transistores da PDN, já casos de descasamentos, por não terem um método de compensação, acabam por degradar a confiabilidade do circuito. Na avaliação da área ocupada por célula, a topologia MCML mostrou consumir mais área do que a topologia CMOS. / This work proposes a simulation-based methodology to design MOS Current-Mode Logic (MCML) gates and addresses the tradeoffs of the MCML versus static CMOS circuits. MCML is a design style developed focusing in a high-speed logic circuit. This logic style works with the principle of steering a constant bias current through a fully differential network of input transistors. The proposed methodology uses the quadratic transistor model to find the first design solution, through SPICE simulations, make decisions and resizes the gate to obtain the required solution. The method considers a uniform sizing of the pull-down network transistors. The target solution is the best propagation delay for a predefined gate noise margin. We design MCML gates for three different process technologies (XFAB XC06, IBM130 and PTM45), considering gates up to three inputs. We compare the solutions of the proposed methodology against commercial optimization software, Wicked™, that considers different sizing for PDN differential pairs. The solutions of the software results in a 20% of improvement, when compared to the proposed methodology, in the worst case input delay for the XFAB XC06 technology, and 3% in IBM130. We demonstrate through ring oscillators simulations that MCML gates are better for high speed and small logic path circuits when compared to the CMOS static gates. Moreover, by using MCML frequency dividers we obtained a maximum working frequency that almost doubles the frequency achieved by CMOS frequency dividers, dissipating less power than static CMOS circuits. We demonstrate through a reliability analysis that the analog behavior of MCML gates makes them susceptible to PVT variations. The global variations are compensated by the bias control circuits and with the increase of the PDN transistor width. This procedure compensates the gain loss of these transistors in a worst case variation. In other hand, this increasing degrades the propagation delay of the gates. The MCML gates reliability is heavily affected by the mismatching effects. The difference of the mirrored bias current and the mismatching of the differential pairs and the PUN degrade the design yield. The results of the layout extracted simulations demonstrate that MCML gates performs a better propagation delay performance over gates that depend on complexes pull-up networks in standard CMOS implementation, as well as multi-stages static CMOS gates. Considering the gate layout implementation we demonstrate that the standard structures of pull-up and bias current mirror present in the gate are prejudicial for the MCML gate area.

abstract: High-efficiency DC-DC converters make up one of the important blocks of state-of-the-art power supplies. The trend toward high level of transistor integration has caused load current demands to grow significantly. Supplying high output current and minimizing output current ripple has been a driving force behind the evolution of Multi-phase topologies. Ability to supply large output current with improved efficiency, reduction in the size of filter components, improved transient response make multi-phase topologies a preferred choice for low voltage-high current applications. Current sensing capability inside a system is much sought after for applications which include Peak-current mode control, Current limiting, Overload protection. Current sensing is extremely important for current sharing in Multi-phase topologies. Existing approaches such as Series resistor, SenseFET, inductor DCR based current sensing are simple but their drawbacks such low efficiency, low accuracy, limited bandwidth demand a novel current sensing scheme. This research presents a systematic design procedure of a 5V - 1.8V, 8A 4-Phase Buck regulator with a novel current sensing scheme based on replication of the inductor current. The proposed solution consists of detailed system modeling in PLECS which includes modification of the peak current mode model to accommodate the new current sensing element, derivation of power-stage and Plant transfer functions, Controller design. The proposed model has been verified through PLECS simulations and compared with a transistor-level implementation of the system. The time-domain parameters such as overshoot and settling-time simulated through transistor-level implementation is in close agreement with the results obtained from the PLECS model. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017