A heavy duty vehicle looses approximately 30-40 % of the energy in the fuel as waste heat through the exhaust system. Recovering this waste heat would make the vehicle meet the legislative and market demands of emissions and fuel consumption easier. This recovery is possible by transforming the waste heat to electric power using a thermoelectric generator. However, the thermoelectric generator electric characteristics makes direct usage of it unprotable, thus an electric power conditioner is necessary. First a study of dierent DC-DC converters is presented, based on that the most suitable converter for thermoelectric application is determined. In order to maximize the harvested power, maximum power point tracking algorithms have been studied and analyzed. After the investigation, the single ended primary inductor converter was simulated and implemented with a perturb and observe algorithm, and the incremental conductance algorithm. The converter was tested with a 20 W thermoelectric generator, and evaluated.The results show that the incremental conductance is more robust and stable compared to the perturb and observe algorithm. Further on, the incremental conductance also has a higher average eciency during real implementation.

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With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel's roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs.

Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit.

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