1-bit analog-to-digital conversion is very attractive for low-complexity communications receivers. A major drawback is, however, the small spectral efficiency when sampling at symbol rate. This can be improved through oversampling by exploiting the signal distortion caused by the transmission channel. This paper analyzes the achievable data rate of band-limited communications channels that are subject to additive noise and inter-symbol-interference with 1-bit quantization and oversampling at the receiver. It is shown that not only the channel noise but also the inter-symbol-interference can be exploited to benefit from oversampling.

Window decoding schedules are very attractive for message passing decoding of spatially coupled LDPC codes. They take advantage of the inherent convolutional code structure and allow continuous transmission with low decoding latency and complexity. In this paper we show that the decoding complexity can be further reduced if suitable message passing schedules are applied within the decoding window. An improvement based schedule is presented that easily adapts to different ensemble structures, window sizes, and channel parameters. Its combination with a serial (on-demand) schedule is also considered. Results from a computer search based schedule are shown for comparison.

In this paper, we analyze the achievable secrecy rates in the two-hop wiretap channel with four nodes, where the transmitter and the receiver have multiple antennas while the relay and the eavesdropper have only a single antenna each. The relay is operating in amplify-and-forward mode and all the channels between the nodes are known perfectly by the transmitter. We discuss different transmission and protection schemes like artificial noise (AN). Furthermore, we introduce interference neutralization (IN) as a new protection scheme. We compare the different schemes regarding the high-SNR slope and the high-SNR power offset and illustrate the performance by simulation results. It is shown analytically as well as by numerical simulations that the high SNR performance of the proposed IN scheme is better than the one of AN.

A 2TnC ferroelectric memory gain cell consisting of two transistors and two or more ferroelectric capacitors (FeCAP) is proposed. While a pre-charge transistor allows to access the single cell in an array, the read transistor amplifies the small read signals from small-scaled FeCAPs that can be operated either in FeRAM mode by sensing the polarization reversal current, or in ferroelectric tunnel junction (FTJ) mode by sensing the polarization dependent leakage current. The simultaneous read or write operation of multiple FeCAPs is used to realize compute-in-memory (CiM) algorithms that enable processing of data being represented by both, non-volatilely internally stored data and externally applied data. The internal gain of the cell mitigates the need for 3D integration of the FeCAPs, thus making the concept very attractive especially for embedded memories. Here we discuss design constraints of the 2TnC cell and present the proof-of-concept for realizing versatile (CiM) approaches by means of electrical characterization results.

In heterogeneous dense networks where spectrum is shared, users' privacy remains one of the major challenges. On a multi-antenna relay-assisted multi-carrier interference channel, each user shares the spectral and spatial resources with all other users. When the receivers are not only interested in their own signals but also in eavesdropping other users' signals, the cross talk on the spectral and spatial channels becomes information leakage. In this paper, we propose a novel secrecy rate enhancing relay strategy that utilizes both spectral and spatial resources, termed as information leakage neutralization. To this end, the relay matrix is chosen such that the effective channel from the transmitter to the colluding eavesdropper is equal to the negative of the effective channel over the relay to the colluding eavesdropper and thus the information leakage to zero. Interestingly, the optimal relay matrix in general is not block-diagonal which encourages users' encoding over the frequency channels. We proposed two information leakage neutralization strategies, namely efficient information leakage neutralization (EFFIN) and local-optimized information leakage neutralization (LOPTIN). EFFIN provides a simple and efficient design of relay processing matrix and precoding matrices at the transmitters in the scenario of limited power and computational resources. LOPTIN, despite its higher complexity, provides a better sum secrecy rate performance by optimizing the relay processing matrix and the precoding matrices jointly. The proposed methods are shown to improve the sum secrecy rates over several state-of-the-art baseline methods.

In der vorliegenden Arbeit werden eine sichere FPGA-Stellwerksplattform und ein Transformationsverfahren entwickelt, mit dem die Schaltungen bestehender Relaisstellwerke in eine FPGA-Logik überführt werden können. Die FPGA-Stellwerksplattform ersetzt die Innenanlage eines Relaisstellwerks. Ihre Schnittstellen entsprechen den bisherigen Schnittstellen am Kabelabschlussgestell und zur Bedien- und Meldeeinrichtung. Damit ist eine einfache Migration bestehender Stellwerke möglich. Das Sicherheitskonzept basiert auf einer zweikanaligen Struktur mit sicherem Vergleicher und zusätzlichen Selbsttests zur schnellen, datenflussunabhängigen Ausfalloffenbarung. Die erreichbare Gefährdungsrate liegt im Bereich von SIL 4 und entspricht damit dem Sicherheitsziel für Stellwerke der Deutschen Bahn. Die Transformation sieht eine Trennung der Stellwerkslogik in Logik- und Leistungsteil vor. Der Logikteil wird auf dem FPGA realisiert. Die im Leistungsteil verbliebenen Kontakte und Überwacherrelais werden durch sichere Stellteile ersetzt. Die logischen Ansteuerbedingungen der Relais werden in Schaltnetze überführt. Die gesteuerten Relais werden durch Instanzen generischer Zustandsmodelle ersetzt. Für jeden verwendeten Relaistyp wurde ein entsprechendes Modell entwickelt, das bei der Transformation als Baustein eingesetzt werden kann. Die generischen Zustandsmodelle berücksichtigen auch die sicherheitsrelevanten konstruktiven Eigenschaften der Relais. So wird bei der Auftrennung einer Schaltung in Logik- und Leistungsteil sichergestellt, dass die in getrennte Schaltungsteile überführten Öffner und Schließer eines Relais nie gleichzeitig geschlossen sein können (Zwangsführung der Kontakte). Dies ist eine Voraussetzung für die Beibehaltung der sicherheitsrelevanten Funktionsbedingungen der Originalschaltung. Das Transformationsverfahren und die implementierten Mechanismen zur Ausfalloffenbarung sind unabhängig von der Anwenderlogik und vom gewählten Schaltkreistyp. Damit kann der generierte VHDL-Code bei Obsoleszenz eines Schaltkreises auch auf andere FPGA-Typen portiert werden. In einer Ressourcenabschätzung wird gezeigt, dass der gewählte Lösungsansatz geeignet ist, die Schaltungen kleinerer Relaisstellwerke vollständig auf einem FPGA zu realisieren. Die Anwendung des vorgestellten Verfahrens wird am Beispiel der Weichengruppe des Stellwerkstyps GS II DR demonstriert. Das Transformationsverfahren ist aber auch für andere Stellwerksbauformen geeignet. Dabei ist es unerheblich, ob diese nach dem tabellarischen Verschlussplanprinzip oder dem Spurplanprinzip arbeiten.

Though ferroelectric HfO₂ thin films are now well characterized, little is currently known about their grain substructure. In particular, the formation of domain and phase boundaries requires investigation to better understand phase stabilization, switching, and phase interconversion. Here, scanning transmission electron microscopy is applied to investigate the atomic structure of boundaries in these materials. It is found that orthorhombic/orthorhombic domain walls and coherent orthorhombic/monoclinic interphase boundaries form throughout individual grains. The results inform how interphase boundaries can impose strain conditions that may be key to phase stabilization. Moreover, the atomic structure near interphase boundary walls suggests potential for their mobility under bias, which has been speculated to occur in perovskite morphotropic phase boundary systems by mechanisms similar to domain boundary motion.

Electron beam powder bed fusion (EB-PBF) is a powder-bed fusion additive manufacturing process, which is suitable for fabricating high-performance parts for a wide range of industrial applications, such as medical and aerospace. Due to its deep curing capabilities, the metastable β-alloy Ti-5Al-5Mo-5V-3Cr (Ti-5553) is currently mostly used in the landing gear of airplanes. However, its great mechanical properties make it also attractive for small, complex, and load-bearing components. In this study, nine melting parameter sets, combining different scanning speeds and beam currents, were used in the EB-PBF ARCAM A2X system. Furthermore, the correlation between the microstructure and the mechanical properties was investigated and analyzed by applying µ-focus computer tomography and microscopic methods (optical, SEM/EDS). A significant influence of the different melting parameters on the microstructure as well as on the mechanical performance was found. In a subsequent step, three melting parameters were selected and the specimens were heat-treated (BASCA, STA) for further investigation. The experimental results of this work indicate that Ti-5553 parts can be manufactured successfully with high quality (ρ > 99.60%), and post-processing heat-treatments can be used to modify the microstructure in such a way that the parts are suitable for a large variety of possible applications.

Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of open-source RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for 8 x 32-bit tiles and 316 MOPS for 8 x 64-bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex UltrascaleC FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.:1 Introduction 2 Fundamentals 2.1 Non-volatile semiconductor memories 2.2 Emerging memory concepts 2.3 Ferroelectric memories 3 Characterisation methods 3.1 Memory characterisation tests 3.2 Ferroelectric memory specific characterisation tests 3.3 Trapping characterisation methods 3.4 Microstructural analyses 4 Sample description 4.1 Metal-insulator-metal capacitors 4.2 Ferroelectric field effect transistors 5 Stabilisation of the ferroelectric properties in Si:HfO2 thin films 5.1 Impact of the silicon doping 5.2 Impact of the post-metallisation anneal 5.3 Impact of the film thickness 5.4 Summary 6 Electrical properties of the ferroelectric Si:HfO2 thin films 6.1 Field cycling effect 6.2 Switching kinetics 6.3 Fatigue behaviour 6.4 Summary 7 Ferroelectric field effect transistors based on Si:HfO2 films 7.1 Effect of the silicon doping 7.2 Program and erase operation 7.3 Retention behaviour 7.4 Endurance properties 7.5 Impact of scaling on the device performance 7.6 Summary 8 Trapping effects in Si:HfO2-based FeFETs 8.1 Trapping kinetics of the bulk Si:HfO2 traps 8.2 Detrapping kinetics of the bulk Si:HfO2 traps 8.3 Impact of trapping on the FeFET performance 8.4 Modified approach for erase operation 8.5 Summary 9 Summary and Outlook