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Reconfigurable computing has the potential for providing significant performance increases to a number of computing applications. However, realizing these benefits requires digital design experience and knowledge of hardware description languages (HDLs). While a number of tools have focused on translation of high-level languages (HLLs) to HDLs, the tools do not always create optimized digital designs that are competitive with hand-coded solutions. This work describes an automatic optimization in the C-to-HDL transformation that reorganizes operations between pipeline stages in order to reduce critical path lengths. The effects of this optimization are examined on the MD5, SHA-1, and Smith-Waterman algorithms. Results show that the optimization results in performance gains of 13%-37% and that the automatically-generated implementations perform comparably to hand-coded implementations.

This thesis started as an initiative from one of the co-authors that previously worked at SAAB AB during summer 2018. During the summer she worked with the design process of In-process part Definition (IPPD) and an interest emerged for making it more efficient. The design process of IPPD (DPOI) is where a design article, designed in CATIA, become manufacturable and adapted for assembly. The DPOI can be seen as the interface between the department of Airframe development and Production at SAAB AB. The first step was to investigate the current DPOI and conduct a pre-study to find time-consuming activities.  The pre-study consisted of five interviews, an observational study and a time study were the aims was to collect employees' own opinions, approve a pre-defined workflow divided into twelve elements and find problem areas. Element 1.0-11.0 is tasks within the DPOI and element 12.0 is the first step in the review process called Checker. Element 4.0 and 8.0 were divided further into parallel activities where the operators in the time study performs either, e.g., E4.0 (macro) or E4.1 (manually). To find time-consuming activities a time study was performed. The authors of this thesis acted observers and clocked each element while three operators denoted A-C designed 24 IPPDs. The results from the time study showed that elements 1.0, 3.0, 4.1 and 7.0 were time-consuming and E4.1 had potential to become automated. The selection of 2-3 problems was carried out through two Weighted Sum Models (WSM) where criteria was defined and solutions was listed. Each solution was weighted to each criterion and got a total grade. The selected problems, based on the total grade, were: Documents and Combined macro. Documents and manuals for scenario 5, 6 and the entire design process of IPPD was developed to make new employees learning process more efficient. A draft macro for scenario 5 and new complete macros for scenario 1 and 6 was developed and used in the comparative study. The comparative study was conducted like the previous time study but instead the new developed macros was used to make E4.0 more efficient and eliminate E4.1. In the comparative study only E4.0 was clocked for all 24 IPPDs in the time study. The result showed that E4.0 has become average 60% more efficient for all IPPDs and the total time with the new developed macros for E4.0 vs E4.1 has become 14,3% more efficient. Problems and time-consuming activities has been found and improved. The performed comparative study shows that the DPOI can be minimized further in terms of time; there are possibilities to make more elements from the DPOI automated.

<p>This master thesis describes the creation of a fully parameterizable design tool, intended for automatic generation of standard cell layouts from basic schematic information. The thesis covers general background on programs for automatic layout generation, standard cells and basics in IC design. Algorithms commonly used in various parts of such programs are presented, and the ones used to implement the tool are described in depth.</p>

<p>This master thesis tells about Aptivia, what it contains and how i works (inluding a manual). As well as problems with it.</p><p>It also consists of an evaluation of a Place and Route tool, telling the discovered problems with it and ideas for solving them.There is also several different descriptions of the code that implements the Place and Route tool.</p>

The demand for customised products that meet different markets and different customers is steadily increasing. Also, the demand for shorter lead times for the delivery of these customised products puts strains on design departments whose work tends to become increasingly repetitive. At the same time, designing variants takes time from innovative, original design, and/or problem-solving tasks. A powerful tool in the endeavour to cut lead times, workloads, and ultimately costs in order to become more competitive in an increasingly globalised market is Design Automation. Automating tedious and repetitive design tasks will free the designers to focus on the tasks that require skill, creativity, intuition, and cooperation to be solved. Consequently, seeing a need for design automation systems is not difficult. What becomes a lot more difficult is identifying the type, scope, and format of the system implementation, as well as the actual design tasks and activities to support or automate. Therefore, there is a need for structured and systematic approaches for the realisation and implementation of design automation systems. This research work is aimed at presenting such approaches, methods, and aids. It also addresses the importance of identifying the exact tasks to be automated. This has to be done in order to find the method and implementations best suited for solving the tasks, something that is especially important for companies whose human and financial resources might not allow them to invest in a system with functionality that vastly exceeds their actual needs. The contribution of this work is a structured method for planning for design automation implementation. First, the design process is discussed from an automation perspective. Following this is a presentation of a framework of design automation. This framework has the purpose of serving as a common base for consensual discussions about design automation. In addition, it supports the setting-up of system specifications. The framework is followed by the introduction of a set of identifiers of system needs and potentials, focusing on the existing processes that need to be broken down and identified in order to specify the tasks to be automated. Following this is a set of criteria of system characteristics, focusing on properties of the intended system implementation. Finally, some realisation and implementation issues are addressed and exemplified through a number of pilot system implementations. The presented method for planning design automation, together with the presented framework of design automation, provides implementers with issues to address regarding potential, need, scope, and format of system implementations. Further, it supports the weighing of desired system characteristics in order to find the right balance between system complexity and functionality.

The huge demand for electronic devices has driven semiconductor companies to create better products in terms of area, speed, power etc. and to deliver them to market faster. Delay to market can result in lost opportunities. The length of the design cycle directly affects the time to market. However, inadequate time for design and verification can cause bugs that will cause further delays to market and correcting the error after manufacturing is very expensive. A bug in an ASIC found after fabrication requires respinning the mask at a cost of several million dollars. Even as the pressure to reduce the length of the design cycles grows, the size and complexity of digital hardware circuits have increased, which puts even greater pressure on design and verification productivity. Pipelining is one optimization technique which has contributed to the increased complexity in hardware design. Pipeline increases throughput by overlapping the execution of instructions. It is a challenge to design and verify pipelines because the specification is written to describe how instructions are executed in sequence while there can be multiple instructions being executed in a pipeline at one time. The overlapping of instructions adds further complexity to the hardware in the form of hazards which arise from resource conflicts, data dependencies or speculation of parcels due to branch instructions. To address these issues, we present PipeNet, a metamodel for describing hardware design at a higher level of abstraction and Bluenose II, a graphical tool for manipulating a PipeNet model. PipeNet is based on a pipeline model in a formal pipeline verification framework. The pipeline model contains arbiters, flow-control state machines, datapath and data-routing. The designer describes the pipeline design using PipeNet. Based on the PipeNet model, Bluenose II generates synthesizable VHDL code and a HOL verification script. Bluenose II's ability to generate HOL scripts turns the HOL theorem prover into Bluenose II's external verification environment. A direct connection to HOL is implemented in the form of a console to display results from HOL directly in Bluenose II. The data structures that represent PipeNet are evaluated for their extensibility to accommodate future changes. Finally, a case study based on an implementation of a two-wide superscalar 32-bit RISC integer pipeline is conducted to examine the quality of the generated codes and the entire design process in Bluenose II. The generation of VHDL code is improved over that provided in Bluenose I, Bluenose II's predecessor.

During the practical use of Design Automation (DA) System in a company, the lack of assistance from either documentation work about the whole system or management of knowledge could bring out some obstacles when engineers reuse existing knowledge and information. The purpose of this project is to explore an approach of documentation and knowledge management in DA System. The study is mainly based on the actual case of seat heater DA system developed by JTH. Based on preset functional requirement for the potential solution, several principles and methods of documentation and knowledge management are introduced such as MOKA, CommonKADS, SysML and PVM. A number of useful applications such as DRed (Design Rationale Editor), PC PACK, Sementic MediaWiki and Product Model Manager became candidates solutions for this project. The selection of final approach was Sementic MediaWiki, and this is based on the comparison of the result from evaluation of functionality of each application. Due to specificity of documentation on the DA system, the “process based” approa­ch­ had been used for structuring system included knowledge instead of using a systematical method like either MOKA or CommonKADS completely. Setting up interconnection between different knowledge objects was one of the most important tasks in this project because it enables capturing and retrieving of knowledge. Sementic MediaWiki, a powerful text representative and web-based tool has been used as a platform of representing the whole knowledge and information. With its implementation, the performance of Sementic MediaWiki had been tested accor­ding to the preset functional requirement. After a slight refine process to the solution, the satisfactory result had been achieved, and also proved the applicability of Sementic Wiki in such kind of project.

This master thesis describes the creation of a fully parameterizable design tool, intended for automatic generation of standard cell layouts from basic schematic information. The thesis covers general background on programs for automatic layout generation, standard cells and basics in IC design. Algorithms commonly used in various parts of such programs are presented, and the ones used to implement the tool are described in depth.

This master thesis tells about Aptivia, what it contains and how i works (inluding a manual). As well as problems with it. It also consists of an evaluation of a Place and Route tool, telling the discovered problems with it and ideas for solving them.There is also several different descriptions of the code that implements the Place and Route tool.