The main purpose of this thesis is to research High-Order Sigma-Delta Analog-to-Digital converter for precision measurement, a PI compensator and a third-order Sigma-Delta modulator has been proposed based on a second-order Sigma-Delta modulator. In accordance with the analysis result of frequency domain and time domain of system, we use third-order model because of better response with auxiliary software to simulate and implement the system, then measure modulator output variance for input variation. This converter circuit demonstrates that it can achieve the requirements of precision and linearity which the measure instrument demands.

The digital product increases widely and vastly. Because we live in the analog world, we require a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed and low power analog to digital converter. In this thesis, the circuits are designing with TSMC.18 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit.

As the rapid development of the wireless communication system and mobile video devices, the integrated chip with low power consuming and high conversion efficiency is widely needed. ADC and DAC are playing an important role in these applications. The aim of this thesis is to verify a post-correction method which is used for improving the performance of ADC. First of all, this report introduces the development and present status of ADC, and expatiate its important parameters from two different classes (static performance and dynamic performance). Based on the fundamental principle, the report then focuses on the dynamic integral non-linearity modeling of ADC. Refer to this model, one post-correction method is described and verified. Upon the face of post-correction, this method is to modify the output signals which have been converted from analog to digital format by adding a correction term. Improvement made by the post-correction needs to be checked out. Thus the performance analysis mainly relay on the measures of total harmonic distortion and signal to noise and distortion ratio is also included in this thesis.

Because IC (Integrated Circuit) has some good features like: little, low power consumption, and high stable, so it already popularly applied to our daily life. Operation is one of the main functions of IC, and now operate function achieve in digital mode of many IC products. Although digital circuits have many advantages, but we live in the analog world, natural signals are all analog. Digital circuits can¡¦t direct process analog signals, and therefore we have a requirement of analog-to-digital converter. As time goes by, IC technology has made great progress; digital circuits have faster process ability, and we also require a high speed analog-to-digital converter. Besides, in order to achieve higher picture quality and clearer voice, we also require a high resolution analog-to-digital converter. For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed, high resolution and low power analog-to-digital converter. In this thesis, the circuits are designing with TSMC.18£gm 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit. Keywords: ADC, Analog-to-Digital Converter, pipeline, low power, amplifier, comparator.

The emergence of bandwidth-intensive services has created a need for high speed and high resolution data converters. Towards this end, system level design of a continuous-time sigma-delta modulator achieving 11 bits resolution over 100 MHz signal bandwidth by using a feed-forward topology is presented. The system is first built in the Simulink environment in MATLAB. The building blocks in the loop filter are modeled with non-idealities, and specifications for these blocks are obtained by simulations. An operational transconductor amplifier (OTA) with 100 mS transconductance, 70 dB linearity, and 34.2 mW power dissipation is designed to be used in the loop filter. Simulation results indicate that the 5th order loop filter implemented in the feed-forward architecture in transistor level shows lower power consumption, 105 mW, compared to the loop filter implemented by feedback architecture, 152 mW.

A 2.5V 8-bit 100MSample/sec folding and interpolation analog to digital converter is described in this thesis. First, a cascoding folding amplifier is used for improve power consumption. The differential pairs of the folding amplifier are cascoded to reduce the numbers of reference current source, so the power consumption is reduced. In order to reduce more power consumption, we drop the power supply down to 2.5V. However, the power supply is not large enough to keep the folding amplifier working normally and it causes the output signal aberration. Hence, we propose a back-end amplifier to connect the folding amplifier to overcome the problem. Therefore, the power consumption of all circuit is reduced to 15.292mW. Moreover, the capacitive loading at the output of the cascoded differential pairs is smaller than that of conventional cascaded differential pairs, and we employ a distributed folding technique to reduce the folding factors of each folding amplifier. Therefore, we improve the frequency multiplication effect to increase the analog input signal bandwidth. Beside, in order to heave the input signal range of the voltage mode comparator, we employ an n-channel input stage. Because the input signal range of n-channel is higher than that of p-channel input stage. By using these techniques, the input signal bandwidth and the power consumption of overall circuit are improved greatly. The proposed analog to digital converter is designed by TSMC 0.35£gm 2P4M CMOS process, and it operates at 2.5V power supply voltage with 1V to 2.4V reference voltage. The simulation results show that the power consumption is 15.292mW, DNL is +/- 0.55LSB, and INL is 1.7LSB ~ -0.8LSB.

In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long time operation. As a fundamental building block of ADC, comparator should support a tightened power budget. Therefore, developing low-power design techniques for comparator is becoming more and more important. As an alternative to the conventional voltage-mode comparator, this thesis proposed an energy efficient time-domain comparator, which uses digital circuits to process analog signals by representing them as timing information. The proposed time-domain comparator has three main features: comparing on both clock edges (rising/falling), asynchronous comparison and 2-bit/step comparison. With these features, power consumption of the comparator can be effectively reduced. For verification, the proposed time-domain comparator is fabricated in IBM 0.18um CMOS technology in comparison with other two conventional time-domain comparators working at 100kS/s sampling rate and 8-bit resolution. The achieved power consumption of the proposed time-domain comparator is 50nW, which is much lower than 84nW and 285nW of the other two time-domain comparators.

Digital silicon photomultipliers (dSiPMs) and single-photon avalanche diode (SPAD) imagers are optical sensing systems formed from the integration of time-to-digital converters (TDCs) with arrays of highly sensitive photodetectors known as SPADs. TDCs are high-performance mixed-signal circuits capable of timestamping events with picosecond level resolution. The digital operation mechanisms of SPADs allow for their outputs to be sent to TDCs, where the timestamps of individual photon detections are recorded. In recent years, time-resolved SPAD-based sensors have been a heavily studied topic due to their exceptional performance potential in biomedical imaging applications, including time-of-flight (ToF) positron emission tomography (PET), fluorescence lifetime imaging microscopy (FLIM), and diffuse optical tomography (DOT). This work targets the optimization of these sensors in low-cost standard complementary metal-oxide-semiconductor (CMOS) processes. Firstly, this thesis provides a detailed review of the work accomplished in CMOS TDCs and their integration in SPAD-based sensors. Next, a feedback time amplification TDC was designed and tested in the TSMC 65 nm process that can achieve < 5 ps timing resolution in a very compact area of 0.016 mm2. The design is then described for a multi-time-gated array of p+/n-well SPADs that aims to mitigate SPAD dark noise while providing high-speed imaging by applying shifted gate windows simultaneously to an array of SPADs. The p+/n-well SPAD is first characterized in a passive quench configuration where it demonstrated a maximum dark count rate of 44.9 kHz, 18.1% peak PDP at 420 nm, and 0.82 ns timing jitter at a 0.7 V excess bias. While the current multi-time-gated prototype is not fully functional, the measurement results for individual pixels of the multi-time-gated array showed a 3.25 ns median gate window with a 2.2x 10-4 dark count probability for a 0.7 V excess bias, with 440 ps timing resolution and ~1 LSBrms timing jitter. Based on the results, limitations of the current design and sources for future improvement are then discussed in detail. / Thesis / Master of Applied Science (MASc) / Medical imaging plays a key role in the diagnosis of diseases like cancer, and as such, the optimized performance of medical imaging systems is a large area of research. Recently, highly sensitive photodetectors known as single-photon avalanche diodes (SPADs) were integrated with high-performance timing circuits known as time-to-digital converters (TDCs) to form digital silicon photomultipliers (dSiPMs) and SPAD imagers. DSiPMs and SPAD imagers are capable of timestamping the detection of individual photons with a very high level of accuracy in order to generate biomedical images. This thesis focuses on the design and measurement of these sensors using standard fabrication processes with the aim of working towards high-performance medical imaging sensors at a low cost. Firstly, we review the results achieved in TDCs and SPAD-based sensors within the recent literature. Following that, we present the design and performance results of a custom-designed TDC that aims to achieve state-of-the-art performance within a small area in order to maintain low-cost and optimal integration with SPADs. Next, the design is described for an array of custom time-gated SPADs with integrated TDCs. Finally, the SPAD is characterized in two different configurations to identify sources of improvement for future design iterations.

Error correction codes are a means of including redundancy in a stream of information bits to allow the detection and correction of symbol errors during transmission. The birth of error correction coding showed that Shannon's channel capacity could be achieved when transmitting information through a noisy channel. Turbo codes are a very powerful form of error correction codes that bring the performance of practical coding even closer to Shannon's theoretical specifications. Bit-error-rate (BER) performance and power dissipation are two important measures of performance used to characterize communication systems. Subject to the law of diminishing returns, as the resolution of the analog-to-digital converter (ADC) in the decoder increases, BER improves, but power dissipation increases. The number of decoding iterations has a similar effect on the BER performance and power dissipation of turbo coded systems. This is significant since turbo decoding is typically practiced in a fixed iterative manner, where all transmitted frames go through the same number of iterations. This is not always necessary since certain "good" frames would converge to their final bits within a few iterations, and other "bad" frames never do converge. In this thesis, we investigate the technical feasibility of adapting the resolution of the ADC in the decoder, and the number of decoding iterations, in order to obtain the best trade-off possible between BER performance and power dissipation in a communication system. With the aid of computer-aided simulations, this thesis investigates the performance and practical implementation issues associated with incorporating a variable resolution ADC into the decoder structure of turbo codes. The possibility of further power conservation resulting from reduced decoding computation is also investigated with the use of a recently developed iterative stopping criterion. / Master of Science

Fluorescence lifetime imaging (FLIM) has the potential to provide rapid screening and detection of diseases. However, time-resolved fluorescence measurements require high-performance detectors with single-photon sensitivity and sub-nanosecond time resolution. These systems should also be compact, reliable, inexpensive, and easily deployable for laboratory and clinical applications. It is with these applications in mind that the development of single photon avalanche diodes (SPAD) and time-to-digital converter (TDC) prototype integrated circuits (IC) in standard digital CMOS have been pursued in this thesis. SPAD and TDC ICs were designed and fabricated in 130 nm IBM CMOS technology and then intensively studied. Several different SPAD pixels were modeled and designed, and the electro-optical performance was characterized and comparatively studied. By repurposing existing design layers of a standard CMOS process, the fabricated SPAD pixel test structures achieved up to 20× improvement of dark count rate (DCR) compared to previous designs. Optical measurements also showed up to 10× improvement in the detection limits for low-level light. Detailed dark noise characterization was performed at various temperatures using free-running and time-gated modes of operation. Optimal operating conditions were found for minimal afterpulsing effects. The SPAD’s capability to accurately measure fast fluorescence decays was also demonstrated in a practical setting with the lifetime measurements of two fluorophores, Rhodamine 6G and Ruby crystal, which have fluorescence lifetimes of approximately 4 ns and 3 ms, respectively. A fast and accurate TDC prototype circuit for time-correlated single-photon counting (TCSPC) applications was designed, fabricated and characterized. With a coarse-fine delay line architecture, the TDC size was reduced without compromising its linearity and jitter performance. Extensive characterization of the fabricated SPAD and TDC ICs shows that the measured performance met the stated design goals. / Thesis / Doctor of Philosophy (PhD)