<p> The thesis is concerned with the design, construction and evaluation of an analog to digital converter based on the "cascade" principle. However, this converter requires only one stage, instead of the usual one stage per bit required by conventional cascade converters. This reduction in the number of stages is achieved by storage in analog form, and by feeding the output of the stage back to its input via a switching network. An 8 bit converter that operates up to a clock frequency of 700KHz was built. The converter is shown to have promising possibilities as a low cost general purpose analog to digital converter. </p> / Thesis / Master of Engineering (MEngr)

No description available.

Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this thesis, we investigated an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Furthermore, the RSD cyclic algorithm is insensitive to offsets, allowing simple, low-power comparators. Our ADC is implemented in a 0.35 um CMOS technology with a single-ended 3.3 V power supply. Our ADC has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average of 10 percent less power when the resolution is decreased by two bits. Simulation results indicate our ADC achieves a bit rate of 1.7 MHz and has a SNR of 84 dB for the maximum input frequency of 8.3 kHz. / Master of Science

In this research, a time-based oversampling delta-sigma (ΔΣ) ADC architecture is introduced. This system uses time, rather than voltage or current, as the analog variable for its quantizer, and the noise shaping process is realized by modulating the width of a variable-width digital “pulse.” The ΔΣ loop integrator, the quantizer and digital-to-analog converter (DAC) are all time-based circuits and are implemented using digital gates only. Hence, no amplifier or voltage-based circuit is required. The proposed architecture not only offers a viable for nano-scale ‘digital’ IC technologies, but also enables improved circuit performance compared to the state-of-the-art. This is in contrast to conventional voltage-based analog circuit design, whose performance decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage. The proposed architecture allows all digital implementation after the Voltage to Time Converter (VTC) and merged multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. The novelty of this architecture is digital pulse width processing to implement the ΔΣ modulation. It is realized with small area and potentially can take advantage from the process scaling. A 3-bit prototype of this ADC in 0.18 μm CMOS process is implemented, tested, and presented. With an OSR of 36 and a bandwidth of 2 MHz, it achieves a SNDR of 34.6 dB while consuming 1.5 mA from a 1.8 V supply. The core occupies an area of 0.0275 mm² (110μm × 250μm = 0.0275 mm²). The second generation of the architecture was fabricated in IBM 45 nm SOI process. The oversampling frequency of this system is 705 MHz and oversampling ratio of 64. The expected performance is 7-bit effective resolution for a 5.5 MHz bandwidth while consuming 8mW of power and occupying a core area of less than 0.02 mm² (160μm × 120μm = 0.0192 mm²). / text

This bachelor thesis has been performed at Saab Dynamics AB in Karlskoga, with the purpose to design simulation models and analyze the technology study for distance measurement based on Time Of Flight (TOF) -principle. The distance measurement is implemented by short laser pulses and Time-to-Digital Converter (TDC). This method uses the time difference between when the laser pulse is transmitted to the time when its reflection from an object returns to the detector. With this technology as a starting point for this thesis, an analysis has been made by looking at the subsystems when it gets affected by different parameters. The simulation will give an expected result which has been compared with the measurement results. On this basis a ranking of the parameters according by the influence of the functionality has been delivered. / Det här examensarbetet har utförts vid Saab Dynamics AB i Karlskoga med syftet att modellera och analysera en teknikstudie för avståndsmätning baserad på Time-Of-Flight-principen (TOF-principen). Avståndsmätningen genomförs med korta laserpulser och Time-to-Digital Converter (TDC). Det är en metod för avståndsmätning som baseras på tidsskillnaden från den tidpunkt då laserpulsen skickas från laserdioden till den tidpunkt då fotodioden har detekterat den reflekterade laserpulsen. Med den nya teknikstudien som utgångspunkt för arbetet har en analys på hur avståndsmätarens delsystem påverkats av olika parametrar genomförts där förväntat resultat har jämförts med mätresultat. Med detta som grund har en rangordning av parametrarna efter hur stor inverkan de har på funktionaliteten levererats.

This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few remaining speed bottlenecks in conventional 2D imagers. At the same time, as pixel dark current continues to improve, the resolution requirements on imaging data converters impose very high system-level design challenges. The focus of the presented investigations here is to shed light on methods in Time-to-Digital Converter interpolation of single-slope ADCs. By using high-factor time-interpolation, the resolution of single-slope converters can be increased without sacrificing conversion time or power. This work emphasizes on solutions for improvement of multiphase clock interpolation schemes, following an all-digital design paradigm. Presented is a digital calibration scheme which allows a complete elimination of analog clock generation blocks, such as PLL or DLL in Flash TDC-interpolated single-slope converters. To match the multiphase clocks in time-interpolated single-slope ADCs, the latter are generated by a conventional open-loop delay line. In order to correct the process voltage and temperature drift of the delay line, a digital backend calibration has been developed. It is also executed online, in-column, and at the end of each sample conversion. The introduced concept has been tested in silicon, and has showed promising results for its introduction in practical mass-production scenarios. Methods for reference voltage generation in single-slope ADCs have also been looked at. The origins of error and noise phenomenona, which occur during both the discrete and continuous-time conversion phases in a single-slope ADC have been mathematically formalized. A method for practical measurement of noise on the ramp reference voltage has also been presented. Multiphase clock interpolation schemes are difficult for implementation when high interpolation factors are used, due to their quadratic clock phase growth with resolution. To allow high interpolation factors a time-domain binary search concept with error calibration has been introduced. Although the study being conceptual, it shows promising results for highly efficient implementations, if a solution to stable column-level unit delays can be found. The latter is listed as a matter of future investigations.

No description available.

The objective of this research is to optimize silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS analog circuit building blocks for operation in extreme environments utilizing design techniques. First, negative feedback effects on single-event transient (SET) in SiGe HBT analog circuits were investigated. In order to study the role of internal and external negative feedback effects on SET in circuits, two different types of current mirrors (a basic common-emitter current mirror and a Wilson current mirror) were fabricated using a SiGe HBT BiCMOS technology and exposed to laser-induced single events. The SET measurements were performed at the U.S. Naval Research Laboratory using a two-photon absorption (TPA) pulsed laser. The measured data showed that negative feedback improved SET response in the analog circuits; the highest peak output transient current was reduced by more than 50%, and the settling time of the output current upon a TPA laser strike was shortened with negative feedback. This proven negative feedback radiation hardening technique was applied later in the high-speed 5-bit flash analog-to-digital converter (ADC) for receiver chains of radar systems to improve SET response of the system.

This thesis reports on the design and evaluation of a microprocessor-controlled, high-speed analog-to-digital converter. The processor supervises and manages the digital conversion, split-phase encoding (Manchester) and framing of the input signal. This converter is designed to be applied in an underwater package which will serially transmit sensor data over a fiber optic link to a shore station. This intelligent sensor will provide for ease of future system enhancements. An example would be the implementation of one package to multiplex several analog channels from a local sensor network over the single fiber optic link to the shore station. Keywords: Analog-to-Digital converter, Digital conversion, Split phase encoding, and Manchester. (r.h.) / http://archive.org/details/microprocessorco00schl / U.S. Coast Guard (U.S.C.G.) author.

"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The ‘split ADC’ is a new concept that allows the use of a deterministic, digital, self calibrating algorithm. In this approach, an ADC is split into two paths, producing two output codes from the same input sample. The difference of these two codes is used as the calibration signal for an LMS error estimation algorithm that drives the difference error to zero. The ADC is calibrated when the codes are equal and the output is taken as the average of the two codes. The ‘split’ ADC concept and interleaved architecture are combined in this IC design to form the core of a high speed, high resolution, and self-calibrating ADC system. The dual outputs are used to drive a digital calibration engine to correct for the channel mismatch errors. This system has the speed benefits of interleaving while maintaining high resolution. The hardware for the algorithm as well as the ADC can be implemented in a standard 0.25um CMOS process, resulting in a relatively inexpensive solution. This work is supported by grants from Analog Devices Incorporated (ADI) and the National Science Foundation (NSF). "