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Návrh injekcí zavěšeného kruhového oscilátoru pro aplikaci v systémech LIDAR přímo měřících čas průletu / Injection locked ring oscillator design for application in Direct Time of Flight LIDARFránek, Jakub January 2021 (has links)
Diplomová práce přibližuje systémy LIDAR přímo měřící čas průletu a časově digitální převodníky určené k použití v těchto systémech. Představuje problematiku distribuce hodinových signálů napříč soubory časově digitálních převodníků v LIDAR systémech a věnuje se jednomu z nových řešení této problematiky, které je založené na injekcí zavěšených oscilátorech. Technika injekčního zavěšení oscilátorů je důkladně matematicky popsána. V programu Matlab byl vytvořen simulační model injekcí zavěšeného kruhového oscilátoru, který potvrzuje správnost uvedených analytických predikcí. Ve výrobní technologii ONK65 byl navržen injekcí zavěšený kruhový oscilátor stabilizovaný pomocí smyčky závěsu zpoždění, určený pro implementaci časově digitálního převodníku pro systém LIDAR. Navržený injekcí zavěšený kruhový oscilátor byl verifikován počítačovými simulacemi zohledňujícími vliv procesních, napěťových i teplotních variací. Oscilátor poskytuje specifikované časové rozlišení 50 pikosekund a dosahuje dvakrát nižší hodnoty fázového neklidu než ekvivalentní volnoběžný oscilátor v dané technologii.
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Lokalizace zvukového zdroje / Sound source localizationVélim, Jan January 2013 (has links)
The paper discusses a possibility of localization of a sound source inside a wooden beam. The method is based on measuring signals from two microphones, assuming the sound source lies between the microphones. The position of the sound source is calculated from the delay between the signals. The calculation of the delay is done by correlation of the signals in the frequency range. ARM architecture microcontroller is used to for the calculations.
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Řídicí jednotka indukčního ohřevu / Induction Heating Control UnitVálik, Martin January 2016 (has links)
The text is focused on development induction heating coltroller. The motivation to create such a device was to correct deficiencies and add the necessary functionality for a device of this type. This was achieved mainly by adding the graphic display and USB interface. Graphic TFT display with buttons and a rotary encoder creates user interface. Part of the control unit is also circuit evaluateing temperature from three thermocouples. The paper dealt with the optimal solution for power supply, communication between control unit and power part, way of controlling graphical TFT display and selection of other components. The core is of course, suitable microcontroller, which manage all parts of the device.
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Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor NodesOmran, Hesham 11 1900 (has links)
Energy efficiency is a key requirement for wireless sensor nodes, biomedical implants,
and wearable devices. The energy consumption of the sensor node needs to
be minimized to avoid battery replacement, or even better, to enable the device to
survive on energy harvested from the ambient. Capacitive sensors do not consume
static power; thus, they are attractive from an energy efficiency perspective. In addition,
they can be employed in a wide range of sensing applications. However, the
sensor readout circuit–i.e., the capacitance-to-digital converter (CDC)–can be the
dominant source of energy consumption in the system. Thus, the development of
energy-efficient CDCs is crucial to minimizing the energy consumption of capacitive
sensor nodes.
In the first part of this dissertation, we propose several energy-efficient CDC architectures
for low-energy sensor nodes. First, we propose a digitally-controlled coarsefine
multislope CDC that employs both current and frequency scaling to achieve
significant improvement in energy efficiency. Second, we analyze the limitations of
successive approximation (SAR) CDC, and we address these limitations by proposing
a robust parasitic-insensitive opamp-based SAR CDC. Third, we propose an
inverter-based SAR CDC that achieves an energy efficiency figure-of-merit (FoM)
of 31fJ/Step, which is the best energy efficiency FoM reported to date. Fourth, we propose a differential SAR CDC with quasi-dynamic operation to maintain excellent
energy efficiency for a scalable sample rate.
In the second part of this dissertation, we study the matching properties of small
integrated capacitors, which are an integral component of energy-efficient CDCs. Despite
conventional wisdom, we experimentally illustrate that the mismatch of small
capacitors can be directly measured, and we report mismatch measurements for subfemtofarad
integrated capacitors. We also correct the common misconception that
lateral capacitors match better than vertical capacitors, and we identify the conditions
that make one implementation preferable.
In the third and last part of this dissertation, we investigate the potential of novel
metal-organic framework (MOF) thin films in capacitive gas sensing. We provide
sensitivity-based optimization and simple fabrication flow for capacitive interdigitated
electrodes. We use a custom flexible gas sensor test setup that is designed and built
in-house to characterize MOF-based capacitive gas sensors.
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Fully-Integrated CMOS pH, Electrical Conductivity, And Temperature Sensing SystemAsgari, Mohammadreza January 2018 (has links)
No description available.
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High-Speed Time-Difference CircuitsLi, Shuo 01 January 2013 (has links) (PDF)
This thesis presents time difference (TD) circuits that are important for measuring fluorescence lifetime, building LIDAR systems, and optimizing digital systems. The contribution of this thesis is to present a systematic organization of TD circuits and to present novel designs for digital-to-time conversion (DTC) and time-to-digital conversion (TDC).
Four basic time difference circuits are presented: TD adder, arbiter, time-difference MUX, and time-difference memory. Specifications, symbols, and multiple circuit implementations are presented for each block. Then the basic blocks are combined to form two compound blocks: DTC and TDC. Novel designs are presented for both blocks along with detailed simulation results.
The DTC was fabricated in TSMC’s 0.35um high-voltage process. A printed circuit board was designed to interface the DTC chip to a computer and test instruments. The DTC demonstrated 80ps resolution.
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DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGYHiremath, Vinayashree 08 December 2010 (has links)
No description available.
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A software radio approach to Global Navigation Satellite System receiver designAkos, Dennis M. January 1997 (has links)
No description available.
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Design of a low power 8-bit A/D converter for wireless neural recorder applicationsYang, Jiao 10 July 2017 (has links)
Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues are extremely helpful for curing many neural injuries and cognitive diseases. One method to discover this field is by designing a chip embedded in brains with probes to actual neurons. It is obvious that batteries are not practical for these applications and thereby RF radiation is used as power sources, revealing that chips should operate under a very low power supply. Since neural signals are analog waveforms, analog-to-digital converter (A/D converter, ADC) is the key component in a neural recorder chip.
This thesis proposes the complete design of a low power 8-bit successive approximation register (SAR) A/D converter for use in a wireless neural recorder chip, realizing the function of digitizing a sampled neural signal with a frequency distribution of 10Hz to 10kHz. A modified energy-saving capacitor array in the SAR structure is provided to help save power dissipation. Therefore, the ADC shall operate within a power budget of 20μW maximum from a 1V power source, at a clock frequency of 500kHz corresponding to a conversion rate of 55.5-kS/s. All the circuits are designed and implemented based on the IBM/Global Foundries 8HP 130nm BiCMOS technology. Simulations of schematic and layout versions are done respectively to verify the functionality, linearity and power consumption of the ADC.
Key words: Successive approximation register analog-to-digital converter (SAR-ADC), low power design, energy-saving capacitor array, neural recorder applications
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Architecture, Modeling, and Analysis of a Plasma Impedance ProbeJayaram, Magathi 01 December 2010 (has links)
Variations in ionospheric plasma density can cause large amplitude and phase changes in the radio waves passing through this region. Ionospheric weather can have detrimental effects on several communication systems, including radars, navigation systems such as the Global Positioning Sytem (GPS), and high-frequency communications. As a result, creating models of the ionospheric density is of paramount interest to scientists working in the field of satellite communication.
Numerous empirical and theoretical models have been developed to study the upper atmosphere climatology and weather. Multiple measurements of plasma density over a region are of marked importance while creating these models. The lack of spatially distributed observations in the upper atmosphere is currently a major limitation in space weather research. A constellation of CubeSat platforms would be ideal to take such distributed measurements. The use of miniaturized instruments that can be accommodated on small satellites, such as CubeSats, would be key to acheiving these science goals for space weather.
The accepted instrumentation techniques for measuring the electron density are the Langmuir probes and the Plasma Impedance Probe (PIP). While Langmuir probes are able to provide higher resolution measurements of relative electron density, the Plasma Impedance Probes provide absolute electron density measurements irrespective of spacecraft charging.
The central goal of this dissertation is to develop an integrated architecture for the PIP that will enable space weather research from CubeSat platforms. The proposed PIP chip integrates all of the major analog and mixed-signal components needed to perform swept-frequency impedance measurements. The design's primary innovation is the integration of matched Analog-to-Digital Converters (ADC) on a single chip for sampling the probes current and voltage signals. A Fast Fourier Transform (FFT) is performed by an off-chip Field-Programmable Gate Array (FPGA) to compute the probes impedance. This provides a robust solution for determining the plasma impedance accurately.
The major analog errors and parametric variations affecting the PIP instrument and its effect on the accuracy and precision of the impedance measurement are also studied. The system clock is optimized in order to have a high performance ADC. In this research, an alternative clock generation scheme using C-elements is described to reduce the timing jitter and reference spurs in phase locked loops. While the jitter performance and reference spur reduction is comparable with prior state-of-the-art work, the proposed Phase Locked Loop (PLL) consumes less power with smaller area than previous designs.
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