Outer space is a very harsh environment that can cause electronics to not operate as they were originally intended. Aside from the extreme amount of radiation found in space, temperatures can also change very dramatically in a relatively small time frame. In order to test electronics that will be used in this environment, they first need to be tested on Earth under replicated conditions. Vanderbilt University designed a dewar that allows devices to be tested at these extreme temperatures while being radiated. For this thesis, a test setup that met all of the dewar's constraints was designed that would allow a 12-bit, 16-channel analog-to-digital converter to be tested while inside.

This thesis describes the architecture and implementation of a novel 10-bit hybrid Analog to Digital Converter using Flash and Delay Line concepts. Flash ADCs employ power hungry comparators which increase the overall power consumption of a high resolution ADC. High resolution flash also requires precision analog circuit design. Delay line ADCs are based on digital circuits and operate at low power. Both Flash based ADCs and delay line based ADCs can be used to get a fast analog to digital conversion, but with limited resolution. These two approaches are combined to achieve a 10-bit resolution (4 bits using Flash and 6 bits using delay line) without compromising on speed and maintaining low power operation. Low resolution of Flash also helps in reducing the analog circuit design complexity of the voltage comparators. The ADC was capable of running at 100M samples/s, with an ENOB of 8.82 bits, consuming 8.59mW at 1.8V. / text

The sigma-delta techniques for analog-to-digital conversion have for long been utilized when high precision is needed. Despite the fact that these have been realized by a numerous of different structures, the theory of how to construct a sigma-delta ADC is not very extensive. This thesis will assume that an SFG description of the CRFB sigma-delta modulator has been designed and presents a structured method to obtain a circuit realization of the integrators in a specific modulator. The first activity is to scale the inputs to each integrator in order to make sure that the produced outputs of each integrator is within the output-range of the OTA which is used. The next thing that is presented is an algorithmic way of descending from the SFG design of the modulator down to a switched-capacitor implementation of the system. To be able to continue with the circuit realization, one needs to do a rigorous noise analysis of the modulator, which gives the sizes of the different capacitors in the SC-circuits. The last topic of this thesis is a method to obtain the specifications of the OTA in each integrator.

While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.

While data converters have been around for nearly nighty years, mm-wave data converters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Meanwhile, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may o er repeatable and scalable mm-wave designs. In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold ampli ers, data distribution networks and ip- ops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally veri ed using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.

The objective of this research is to explore high-speed analog-to-digital converters (ADCs) using silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for wireless digital receiver applications. The stringent requirements of ADCs for the high-performance next-generation wireless digital receiver include (1) low power, (2) low cost, (3) wide input signal bandwidth, (4) high sampling rate, and (5) medium to high resolution. The proposed research achieves the objective by implementing high-performance ADC's key building blocks and integrating these building blocks into a complete sigma-delta analog-to-digital modulator that satisfies the demanding specifications of next-generation wireless digital receiver applications. The scope of this research is divided into two main parts: (1) high-performance key building blocks of the ADC, and (2) high-speed sigma-delta analog-to-digital modulator. The research on ADC's building blocks includes the design of two high-speed track-and-hold amplifiers (THA) and two wide-bandwidth comparators operating at the sampling rate > 10 GS/sec with satisfying resolution. The research on high-speed sigma-delta analog-to-digital modulator includes the design and experimental characterization of a high-speed second-order low-pass sigma-delta modulator, which can operate with a sampling rate up to 20 GS/sec and with a medium resolution. The research is envisioned to demonstrate that the SiGe HBT technology is an ideal platform for the design of high-speed ADCs.

[pt] É apresentado um projeto para desenvolvimento de um conversor tempo-digital. O projeto baseia-se no uso de um oscilador como clock de referência, acoplado a uma linha de retardo composta por células de retardo discretas. O retardo total da linha é igual ao período do oscilador, de modo que a cada ciclo apenas um pulso se propaga através da linha. A medida de intervalos de tempo é composta pelo registro da contagem do número de pulsos do oscilador durante o intervalo, mas uma estimativa fina obtida a partir da posição do pulso na linha de retardo no momento de incidência dos sinais delimitadores do intervalo medido. Um estudo detalhado da linha de retardo é mostrado, indicando sua aplicabilidade para a tarefa em questão. Deste estudo fica clara a necessidade de se prever um circuito de acionamento (driver) que realize a interface entre a linha de retardo e os circuitos digitais. Este drive é projetado e testado. Simulações do circuito completo (oscilador, linha reta de retardo, drivers, registrador, codificador e contador) são feitas, demostrando a viabilidade do projeto. Para a implementação do conversor, foram utilizadas uma placa de circuito impresso com quatro camadas e uma interface de aquisição de dados. / [en] It is present a project to develop a Time to Digital Converter. Project is based on use of a oscillator as a clock coupled to a delay line compound by delay cells. The total delay line is equal to the period of oscillator, such for each eycle only a pulse cross the line. Measure of these intervals of time is compound by recording the numbers of oscillators pulses during these intervals, added to a fine estimation from the interval. A detailed study of delay line is showed, indicating its is applicable. It is already important to project a driver that realizes the interface between delay line and the others digital circuits. This driver is projected and tested. Complete circuit is simulated, (oscillator, delay line, register, encoder and counter), showing that project is applicable. A printed board crcuit with four layers and a interface for processing data were developed.

Abstract This thesis describes the development of a high precision time-to-digital converter (TDC) in which the conversion is based on a counter and three-stage stabilised delay line interpolation developed in this work. The biggest design challenges in the design of a TDC are related to the fact that the arrival moment of the hit signals (start and stop) is unknown and asynchronous with respect to the reference clock edges. Yet, the time interval measurement system must provide an immediate and unambiguous measurement result over the full dynamic range. It must be made sure that the readings from the counter and the interpolators are always consistent with very high probability. Therefore, the operation of the counter is controlled with a synchronising logic that is in turn controlled with the interpolation result. Another synchronising logic makes it possible to synchronise the timing signals with multiphase time-interleaved clock signals as if the synchronising was done with a GHz-level clock, and enables multi-stage interpolation. Multi-stage interpolation reduces the number of delay cells and registers needed. The delay line interpolators are stabilised with nested delay-locked loops, which leads to good stability and makes it possible to improve single-shot precision with a single look-up table containing the integral nonlinearities of the interpolators measured at the room temperature. A multi-channel prototype TDC was fabricated in a 0.6 μm digital CMOS process. The prototype reaches state-of-the-art rms single-shot precision of better than 20 ps and low power consumption of 50 mW as an integrated TDC.

This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of a third order ADC with a multi-bit and single bit quantizer are discussed. The advancement in CMOS technology has led to designing as much of electronics systems as possible with the digital circuits and digital signal processing replacing analog processing in most cases. Hence there is a need for digitizing analog signals with analog to digital converter (ADC). In communication systems this needs to be done immediately after the antenna in a receiver system. As this is difficult to implement due to high speed and high power consumption, RF signal is converted to a lower intermediate frequency (IF) and digitized. This work stresses low power implementation of high bandwidth Σ∆ ADCs for digitizing the IF. Design techniques involved in the implementation of a third order continuous time Σ∆ ADC with a 4 bit quantizer as well as a single bit quantizer for wide bandwidth are discussed. Moreover, a third order continuous time audio ADC implementation was also done. The behavioural modelling of the Σ∆ ADC along with clock jitter non-linearity model was developed and the issues in circuit design techniques are addressed. The continuous time ADCs’ major problem, namely, excess loop delay is discussed in detail and an efficient compensation technique for the same is implemented which allows a large reduction of power consumed by the ADC. Choice of loop filter architecture, quantizer and transistor level implementation are given that result in better immunity to offsets and process variations. Both the ADCs have been implemented using UMC 130 nm Mixed-mode RF-CMOS process and the simulation results for the multi-bit ADC gives a peak SNR of 56dB with a dynamic range of 65dB with power consumption of 2mW. The audio ADC achieves a peak SNR of 94.2dB with a dynamic range of 91dB.

This work deals with the collection of data from analog sensors, their storage and display using the Raspberry Pi microcomputer. In more detail it deals with selecting the appropriate analog-to-digital converter, selecting the appropriate storage and database server, web server and application to display the measured data.