<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.</p><p>The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.</p><p>The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.</p><p>A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.</p> / Report code: LiU-Tek-Lic-2005:68.

The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.

Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get more battery life. Because of their ubiquitous nature, ADCs are prime blocks in the signal chain in which power is intended to be reduced. In this thesis, four techniques to reduce power in high speed pipelined ADCs have been proposed. The first is a capacitor and opamp sharing technique that reduces the load on the first stage opamp by three fold. The second is a capacitor reset technique that aids removing the sample and hold block to reduce power. The third is a modified MDAC which can take rail-to-rail input swing to get an extra bit thus getting rid of a power hungry opamp. The fourth is a hybrid architecture which makes use of an asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that prove the efficiency of the proposed techniques are presented. / Graduation date: 2009

The quest for multi-standard and software-defined radio (SDR) receivers calls for high flexibility in the receiver building-blocks so that to accommodate several wireless services using a single receiver chain in mobile handsets. A potential approach to achieve flexibility in the receiver is to move the analog-to-digital converter (ADC) closer to the antenna so that to exploit the enormous advances in digital signal processing, in terms of technology scaling, speed, and programmability. In this context, continuous-time (CT) delta-sigma (ΔƩ) ADCs show up as an attractive option. CT ΔƩ ADCs have gained significant attention in wideband receivers, owing to their amenability to operate at a higher-speed with lower power consumption compared to discrete-time (DT) implementations, inherent anti-aliasing, and robustness to sampling errors in the loop quantizer. However, as the ADC moves closer to the antenna, several blockers and interferers are present at the ADC input. Thus, it is important to investigate the sensitivities of CT ΔƩ ADCs to out-of-band (OOB) blockers and find the design considerations and solutions needed to maintain the performance of CT ΔƩ modulators in presence of OOB blockers. Also, CT ΔƩ modulators suffer from a critical limitation due to their high sensitivity to the clock-jitter in the feedback digital-to-analog converter (DAC) sampling-clock. In this context, the research work presented in this thesis is divided into two main parts. First, the effects of OOB blockers on the performance of CT ΔƩ modulators are investigated and analyzed through a detailed study. A potential solution is proposed to alleviate the effect of noise folding caused by intermodulation between OOB blockers and shaped quantization noise at the modulator input stage through current-mode integration. Second, a novel DAC solution that achieves tolerance to pulse-width jitter by spectrally shaping the jitter induced errors is presented. This jitter-tolerant DAC doesn’t add extra requirements on the slew-rate or the gain-bandwidth product of the loop filter amplifiers. The proposed DAC was implemented in a 90nm CMOS prototype chip and provided a measured attenuation for in-band jitter induced noise by 26.7dB and in-band DAC noise by 5dB, compared to conventional current-steering DAC, and consumes 719µwatts from 1.3V supply.

Continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADC) have emerged as the popular choice to achieve high resolution and large bandwidth due to their low cost, power efficiency, inherent anti-alias filtering and digital post processing capabilities. This work presents a detailed system-level design methodology for a low-power CT ΔΣ ADC. Design considerations and trade-offs at the system-level are presented. A novel technique to reduce the sensitivity of the proposed ADC to clock jitter-induced feedback charge variations by employing a hybrid digital-to-analog converter (DAC) based on switched-capacitor circuits is also presented. The proposed technique provides a clock jitter tolerance of up to 5ps (rms). The system is implemented using a 5th order active-RC loop filter, 9-level quantizer and DAC, achieving 74dB SNDR over 20MHz signal bandwidth, at 400MHz sampling frequency in a 1.2V, 90 nm CMOS technology. A novel technique to improve the linearity of the feedback digital-to-analog converters (DAC) in a target 11-bits resolution, 100MHz bandwidth, 2GHz sampling frequency CT ΔΣ ADC is also presented in this work. DAC linearity is improved by combining dynamic element matching and automatic background calibration to achieve up to 18dB improvement in the SNR. Transistor-level circuit implementation of the proposed technique was done in a 1.8V, 0.18μm BiCMOS process.

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.

Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) technique is designed and implemented in65 nm CMOS technology. The main focus of the thesis work is to implement thepipelined ADC in SI technique and to optimize the pipelined ADC for low power.The ADC has a stage resolution of 3 bits. The proposed architectures combine adifferential sample-and-hold amplifier, current comparator, binary-to-thermometerdecoder, a differential current-steering digital-to-analog converter, delay logic anddigital error correction block. The circuits are implemented at transistor level in 65nm CMOS technology. The static and dynamic performance metrics of pipelinedADC are evaluated. The simulations are carried out by Cadence Virtuoso SpectreCircuit Simulator 5.10. Matlab is used to determine the performance metrics ofADC.

As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modi&#64257;cation improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a con&#64257;gurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications.

<p>The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. </p><p>In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. </p><p>This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.</p>

The object of the thesis was to develop a simple method of the ADC quality evaluation of computer audio systems, which does not require a special apparatus, and software for its realization. To correct the ADC ENOB measurement methodology recommended in the IEEE Std 1241-2000. By applying the recommended method, to investigate possibilities of formation and application of new test analog signals for ADC investigation. To show the possibilities of untraditional computer audio systems application for measurements.