This thesis investigates the feasibility of using a new digital interconnection technology, the IEEE-1394 High Performance Serial Bus, for audio and control data distribution in local and remote music recording studio environments. Current methods for connecting studio devices are described, and the need for a new digital interconnection technology explained. It is shown how this new interconnection technology and developing protocol standards make provision for multi-channel audio and control data distribution, routing, copyright protection, and device synchronisation. Feasibility is demonstrated by the implementation of a custom hardware and software solution. Remote music studio connectivity is considered, and the emerging standards and technologies for connecting future music studio utilising this new technology are discussed. / Microsoft Word / Adobe Acrobat 9.46 Paper Capture Plug-in

Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town,1994 / This thesis describes the design, development and implementation of a digitising workstation for the electronics laboratory that utilises the personal computer.

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This thesis describes the design and implementation of a system to extract meaning from natural language specifications of digital systems. This research is part of the ASPIN project which has the long-term goal of providing an automated system for digital system synthesis from informal specifications. This work makes several contributions, one being the application of artificial intelligence techniques to specifications writing. Also, the work deals with the subset of the English language used to describe digital systems, and the concepts within this domain have been classified into a type hierarchy. Finally, a set of relations has been defined to represent the interrelationships between the concepts of the sublanguage. This work centers around the modeling of information found in natural language specifications of digital systems. The target know ledge representation for the work is the conceptual graph, developed by John Sowa. Conceptual graphs provide a sound theoretical base as well as enough versatility to model the information found in digital system specifications. The transformation from natural language to conceptual graphs is done in two stages. In the first stage, a previously developed context-free English language parser is used to create trees of sentence structure. In the second stage, the trees are processed by a semantic analyzer which uses a conceptual type hierarchy and a database of rules to extract the meaning from the English sentence and create the conceptual graph. The main work of this thesis centers around the semantic analyzer which is written in Quintus Prolog. The semantic analyzer currently contains approximately 380 canonical conceptual graphs that cover usage of over 680 words consisting of over 240 nouns and over 460 verbs. / Master of Science

Partial scan paths improve the testability of digital circuits, and incur minimal costs in the area overhead and test application time. Design constraints may require that a partial scan path include only those flip-flops that provide the greatest improvements in circuit testability. STAFFS, a tool that identifies such flip-flops, has been developed. It uses a statistical testability measure to acquire quantitative data for the controllabilities and observabilities of the nodes of a circuit. It predicts the changes that would occur in the data due to the scanning of specific flip-flops, and uses those predictions to select flip-flops. STAFFS weights the observability data versus the controllability data when selecting flip-flops, and it can efficiently select alternative scan designs for different weights. Experimental results for thirteen sequential benchmark circuits reveal that STAFFS consistently selects scan designs with fault coverages that are significantly higher than those of arbitrarily selected scan designs. / Master of Science

As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in modern low-power microprocessors. This is especially true for ultra-low-voltage (ULV) circuits, where high levels of leakage force designers to chose relatively high threshold voltages, which limits performance. In this thesis, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip. Present power-gating implementations suffer from limitations including non-zero off-state leakage, which can aggregate to a large amount of wasted energy during long idle periods, and high energy overhead, which limits its use to long-term system-wide sleep modes. As this thesis will show however, by vastly increasing the effectiveness of power-gating through the use of emerging technologies, and by implementing aggressive hardware-oriented power-gating policies, leakage in microprocessors can be eliminated to a large extent. This allows the threshold voltage to be lowered, leading to ULV microprocessors with both low switching energy and high performance. The first emerging technology investigated is the Nanoelectromechnical-Systems (NEMS) switch, which is a CMOS-compatible mechanical relay with near-infinite off-resistance and low on-resistance. When used for power-gating, this switch completely eliminates off-state leakage, yet is compact enough to be contained on die. This has tremendous benefits for applications with long sleep times. For example, a NEMS-power-gated architecture performing an FFT per hour consumes 30 times less power than a transistor-power-gated architecture. Additionally, the low on-resistance can lower power-gating area overhead by 36-83\%. The second technology targets the high energy overhead associated with powering a circuit on and off. This thesis demonstrates that a new logic style specifically designed for ULV operation, Sense Amplifier Pass Transistor Logic (SAPTL), requires power-gates that are 8-10 times smaller, and consumes up to 15 times less boot-up energy, compared to static-CMOS. These abilities enable effective power-gating of an SAPTL circuit, even for very short idle periods. Microprocessor simulations demonstrate that a fine-grained power-gating policy, along with this drastically lower overhead, can result in up to a 44\% drop in energy. Encompassing these investigations is an energy estimation framework built around a cycle-accurate microprocessor simulator, which allows a wide range of circuit and power-gating parameters to be optimized. This framework implements two hardware-based power-gating schedulers that are completely invisible to the OS, and have extremely low hardware overhead, allowing for a large number of power-gated regions. All together, this thesis represents the most complete and forward-looking study on power-gating in the ULV region. The results demonstrate that aggressive power-gating allows designers to leverage the very low switching energy of ULV operation, while achieving performance levels that can greatly expand the capabilities of energy-constrained systems. / Ph. D.

This thesis presents teaching fundamentals of digital logic design and VLSI design for freshmen and even for high school students using e-textiles. This easily grabs attention of students as it is creative and interesting. Using e-textiles to project these concepts would be easily understood by students at young age. This involves stitching electronic circuits on a fabric using basic components like LEDs, push buttons and so on. The functioning of these circuits is programmed in Lilypad Arduino. By using this method, students get exposed to basic electronic concepts at early stage which eventually develops interest towards engineering field.

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L'objectif de la thèse est de concevoir et développer un système numérique de combinaison de signaux d'horloges hétérogènes (PPS, horloges atomiques, quartz, ...). Le signal résultant possède une meilleure stabilité que chacune des entrée quelque soit la durée d'intégration et il peut détecter des défaillances chez une des entrées. / The goal of the PhD is to design and build a numerical system capable of combining clock signals from various sources (PPS, atomic clocks, quartz, ...). The output signal will have a better stability at each integration time than any single input signal and it could detect failures in input sources.