This thesis presents an interactive graphics-based FORTRAN program which aids the process of implementing a digital system with wirewrap² circuit boards. Integration of the program into the stream of design process steps is considered and details are presented concerning the development of the interactive graphics subsystem of the program. The user has complete freedom in specifying the location of integrated circuit units on the board. The program provides drawings of both sides of the circuit board, a listing of wirewrap wiring instructions and an equation list of the digital system. Some improvements and refinements of the program are suggested. / M. S.

As the technology scales, there is a need to develop design and optimization algorithms under various scenarios of uncertainties. These uncertainties are introduced by process variation and impact both delay and leakage. For future technologies at the end of CMOS scaling, not only process variation but the device defect density is projected to be very high. Thus realizing error tolerant implementation of Boolean functions with minimal redundancy overhead remains a challenging task. The dissertation is concerned with the challenges of low-power and area digital circuit design under high parametric variability and high defect density. The technology mapping provides an ideal starting point for leakage reduction because of higher structural freedom in the choices of implementations. We first describe an algorithm for technology mapping for yield enhancement that explicitly takes parameter variability into account. We then show how leakage can be reduced by accounting for its dependence on the signal state, and develop a fast gain-based technology mapping algorithm. In some scenarios the state probabilities can not be precise point values but are modeled as an interval. We extended the notion of mean leakage to the worst case mean leakage which is defined as the sum of maximal mean leakage of circuit gates over the feasible probability realizations. The gain-based algorithm has been generalized to optimize this proxy leakage metric by casting the problem within the framework of robust dynamic programming. The testing is performed by selecting various instance probabilities for the primary inputs that are deviations from the point probabilities with respect to which a point probability based gain based mapper has been run. We obtain leakage improvement for certain test probabilities with the interval probability based over the point probability based mapper. Next, we present techniques based on coding theory for implementing Boolean functions in highly defective fabrics that allow us to tolerate errors to a certain degree. The novelty of this work is that the structure of Boolean functions is exploited to minimize the redundancy overhead. Finally we have proposed an efficient analysis approach for statistical timing, which can correctly propagate the slope in the path-based statistical timing analysis. The proposed algorithm can be scaled up to one million paths.

Esta dissertação apresenta os resultados obtidos no estudo do funcionamento dinâmico de uma célula de memória composta por um único transistor SOI MOSFET. Este estudo é baseado nos resultados experimentais observados em dispositivos nMOSFET em tecnologia SOI desenvolvidos no imec, Leuven, Bélgica. Os dados experimentais apresentados foram obtidos no Laboratório de Sistemas Integráveis (LSI) da Escola Politécnica da Universidade de São Paulo (EPUSP) e nos laboratórios AMSIMEC do centro de pesquisa imec, Bélgica. No presente trabalho foi levantado o histórico das memórias dinâmicas, assim como as características fundamentais de uma célula de memória dinâmica de um único transistor, tais como tempo de retenção e margem de sensibilidade, que são definidas e posteriormente verificadas para diferentes tipos de transistores. Inicialmente, foram estudados os mecanismos capazes de promover algum tipo de histerese na curva de corrente de fonte-dreno em função da tensão de porta de um transistor SOI em DC. Por meio destas propriedades, muitas vezes vistas como parasitárias, foi possível explorar o comportamento de um único transistor como célula de memória. Em seguida, passou-se às medidas dinâmicas, momento no qual foi necessário desenvolver um arranjo experimental conveniente de forma que fosse possível medir pulsos da ordem de µA com duração da ordem de 10ns. Assim, uma parte desta dissertação é dedicada à descrição dos problemas e soluções encontrados para viabilizar a medida destes rápidos e pequenos sinais. Foram observados dispositivos com tempos de retenção superiores a 100ms e margens de sensibilidades que ultrapassam 100µA. Finalmente, são apresentadas as conclusões encontradas e as possibilidades para estudos futuros. / This masters thesis presents the results obtained throughout the study of a memory cell composed of a single SOI MOSFET transistor. This study is based on the experimental results observed on SOI nMOSFET devices developed at imec, Leuven, Belgium. The experimental data presented was obtained both at the Laboratório de Sistemas Integráveis (LSI) from the Escola Politécnica da USP (EPUSP) and the AMSIMEC laboratories in the imec research center, Belgium. In this work, the history of dynamic memories as well as the fundamental characteristics of a single transistor dynamic memory cell, such as retention time and sense margin, which are defined and later verified for different transistors, have been analysed. Initially, the mechanisms capable of leading to some sort of hysteresis on the drain-source current as a function of the gate voltage on a SOI transistor operating in DC were studied. Through these properties many times regarded as parasitic it was possible to explore the behavior of a single SOI transistor operating as a memory cell. Afterwards, this work analyzes dynamic measurements, for which it has been necessary to develop an appropriate experimental setup capable of measuring pulses of some µA and lasting approximately 10ns. Therefore, part of this thesis is reserved for the description of the problems and solutions found in order to enable the measurement of these fast and small signals. Devices with retention times larger than 100ms and sense margins surpassing 100µA were measured. Finally, conclusions and possible future studies are presented.

Esta dissertação apresenta os resultados obtidos no estudo do funcionamento dinâmico de uma célula de memória composta por um único transistor SOI MOSFET. Este estudo é baseado nos resultados experimentais observados em dispositivos nMOSFET em tecnologia SOI desenvolvidos no imec, Leuven, Bélgica. Os dados experimentais apresentados foram obtidos no Laboratório de Sistemas Integráveis (LSI) da Escola Politécnica da Universidade de São Paulo (EPUSP) e nos laboratórios AMSIMEC do centro de pesquisa imec, Bélgica. No presente trabalho foi levantado o histórico das memórias dinâmicas, assim como as características fundamentais de uma célula de memória dinâmica de um único transistor, tais como tempo de retenção e margem de sensibilidade, que são definidas e posteriormente verificadas para diferentes tipos de transistores. Inicialmente, foram estudados os mecanismos capazes de promover algum tipo de histerese na curva de corrente de fonte-dreno em função da tensão de porta de um transistor SOI em DC. Por meio destas propriedades, muitas vezes vistas como parasitárias, foi possível explorar o comportamento de um único transistor como célula de memória. Em seguida, passou-se às medidas dinâmicas, momento no qual foi necessário desenvolver um arranjo experimental conveniente de forma que fosse possível medir pulsos da ordem de µA com duração da ordem de 10ns. Assim, uma parte desta dissertação é dedicada à descrição dos problemas e soluções encontrados para viabilizar a medida destes rápidos e pequenos sinais. Foram observados dispositivos com tempos de retenção superiores a 100ms e margens de sensibilidades que ultrapassam 100µA. Finalmente, são apresentadas as conclusões encontradas e as possibilidades para estudos futuros. / This masters thesis presents the results obtained throughout the study of a memory cell composed of a single SOI MOSFET transistor. This study is based on the experimental results observed on SOI nMOSFET devices developed at imec, Leuven, Belgium. The experimental data presented was obtained both at the Laboratório de Sistemas Integráveis (LSI) from the Escola Politécnica da USP (EPUSP) and the AMSIMEC laboratories in the imec research center, Belgium. In this work, the history of dynamic memories as well as the fundamental characteristics of a single transistor dynamic memory cell, such as retention time and sense margin, which are defined and later verified for different transistors, have been analysed. Initially, the mechanisms capable of leading to some sort of hysteresis on the drain-source current as a function of the gate voltage on a SOI transistor operating in DC were studied. Through these properties many times regarded as parasitic it was possible to explore the behavior of a single SOI transistor operating as a memory cell. Afterwards, this work analyzes dynamic measurements, for which it has been necessary to develop an appropriate experimental setup capable of measuring pulses of some µA and lasting approximately 10ns. Therefore, part of this thesis is reserved for the description of the problems and solutions found in order to enable the measurement of these fast and small signals. Devices with retention times larger than 100ms and sense margins surpassing 100µA were measured. Finally, conclusions and possible future studies are presented.

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Vita. / Bibliography: leaves 130-138. / by Michael Allen Krasner. / Ph.D.

Thesis. 1975. M.S.--Massachusetts Institute of Technology. Dept. of Mechanical Engineering. / Bibliography: leaves 194-195. / by Richard James Casler, Jr. / M.S.

Thesis. 1976. M.S.--Massachusetts Institute of Technology. Dept. of Aeronautics and Astronautics. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND AERONAUTICS. / Includes bibliographical references. / by David M. Stofko. / M.S.

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1978. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / B.S.

In measurement, the entire BBP design with the proposed gate-level structures exhibits high robustness in power supply and frequency variations. It can function normally at a minimum of 0.33 V power supply, which is over 100 mV below typical threshold voltage. In the test of the ACRL circuits, the ACRL cells show 30 - 70% delay reduction when compared to the standard static CMOS cells. And the ACRL custom PIE decoder works at the minimum of 0.26 V power supply, which is 40 mV lower than the minimum operating voltage archived by the PIE decoder in the BBP implemented with standard cells. / In this thesis, methodologies and examples are proposed for subthreshold digital circuit design. There is also a full study on subthreshold characteristics of devices and circuits in very-low-voltage operation. The EPC C1G2 baseband processor (BBP) for passive UHF (ultra high frequency) RFID (radio frequency identification) tag is selected as a subthreshold design example, as it is a digital design typified with instable very low supply voltage and requires ultra low power in operation. To tailor the BBP for lower operating voltage in subthreshold region, optimized structures and topologies are proposed in different hierarchical levels. In the system view, the BBP is partitioned according to the clock domain and the constraints of timing. Go down to the RTL and gate level, pipelining, parallelism, clock gating and one-hot state transition are implemented in the logic design according to the actual requirement. In this way energy awareness and power saving are achieved with enhanced robustness to operate in subthreshold region. The BBP with the proposed logic structures has been fabricated in several deep submicron CMOS technologies. Transistor level design is the bottom level for IC designers, the proposed active control ratioed logic (ACRL) is a logic style with fast pull-up network and less capacitance, particularly suitable for the implementation of high fan-in AOI-familiar (and-or-inverter) structure. Some general ACRL cells designs, 32-bit equality comparator and, a custom PIE decoder with ACRL cells, which is the important block of BBP with critical timing, have been fabricated in 130 nm CMOS technology. / Subthreshold designs are required in many actual applications. Especially, the subthreshold digital systems and circuits have become more and more popular in portable devices and passive systems. In conception subthreshold digital circuits are very-low-voltage circuits, they have great reduction of power consumption but suffer from long logic delay as the driving current for logic transition and propagation is greatly reduced. / Shi, Weiwei. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 146-152). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Today a growing number of applications in design engineering, production and environmental testing, and system service require specific analog waveforms and digital patterns. Such requirements are neither satisfactorily nor easily met by the use of standard function or single purpose, custom generators. Traditional methods of waveform generation suffer from undesirable complexity or mediocre performance and are otherwise limited. For the majority of arbitrary waveform generation applications, including medical engineering, modal analysis and electronic engineering, direct digital synthesis techniques are satisfactory. Direct digital synthesis, based generally on periodic retrieval of predetermined amplitude values, may be used to 2 generate such waveforms. Within the limits imposed by the system's maximum sample rate and the Nyquist criteria, any waveform may be produced using these techniques. The objective of this inquiry, within a particular set of constraints, is to extend the cost/performance envelope of direct digital synthesis techniques for the generation of arbitrary waveforms. Performance is enhanced, particularly in the areas of output bandwidth and signal purity.