Indiana University-Purdue University Indianapolis (IUPUI) / Physical activity monitoring using wearable sensors give valuable information about patient's neuro activities. Fall among ages of 60 and older in US is a leading cause for injury-related health issues and present serious concern in the public health care sector. If the emergency treatments are not on time, these injuries may result in disability, paralysis, or even death. In this work, we present an approach that early detect fall occurrences. Low power capacitive accelerometers incorporated with microcontroller processing units were utilized to early detect accurate information about fall events. Decision tree algorithms were implemented to set thresholds for data acquired from accelerometers. Data is then verified against their thresholds and the data acquisition decision unit makes the decision to save patients from fall occurrences. Daily activities are logged on an onboard memory chip with Bluetooth option to transfer the data wirelessly to mobile devices. In this work, a system prototype based on neurosignal activities was built and tested against seven different daily human activities for the sake of differentiating between fall and non-fall detection. The developed system features low power, high speed, and high reliability. Eventually, this study will lead to wearable fall detection system that serves important need within the health care sector. In this work Inter-Integrated Circuit (I2C) protocol is used to communicate between the accelerometers and the embedded control system. The data transfer from the Microcontroller unit to the mobile device or laptop is done using Bluetooth technology.

Indiana University-Purdue University Indianapolis (IUPUI) / The recording and processing of bioelectric signals over the decades has led to the development of many different types of analog filtering and amplification techniques. Meanwhile, there have also been many advancements in the realm of digital signal processing that allow for more powerful analysis of these collected signals. The issues with present acquisition schemes are that (1) they introduce irreversible distortion to the signals and may ultimately hinder analyses that rely on the unique morphological differences between bioelectric signal events and (2) they do not allow the collection of frequencies in the signal from direct-current (DC) to high-frequencies. The project put forth aims to overcome these two issues and present a new scheme for bioelectric signal acquisition and processing. In this thesis, a system has been developed, verified, and validated with experimental data to demonstrate the ability to build an invertible universal amplifier and digital restoration scheme. The thesis is primarily divided into four sections which focus on (1) the introduction and background information, (2) theory and development, (3) verification implementation and testing, and (4) validation implementation and testing. The introduction and background provides pertinent information regarding bioelectric signals and recording practices for bioelectric signals. It also begins to address some of the issues with the classical and present methods for data acquisition and make the case for why an invertible universal amplifier would be better. The universal amplifier transfer function and architecture are discussed and presented along with the development and optimization of the characterization and the inversion, or restoration, filter process. The developed universal amplifier, referred to as the invertible universal amplifier (IUA), while the universal amplifier and the digital restoration scheme together are referred to as the IUA system. The IUA system is then verified on the bench using typical square, sine, and triangle waveforms with varying offsets and the results are presented and discussed. The validation is done with in-vivo experiments showing that the IUA system may be used to acquire and process bioelectric signals with percent error less than to 6% when post-processed using estimated characteristics of and when compared to a standard flat bandwidth high-pass cutoff amplifier.

Le convertisseur analogique-numérique (ADC), fait fonction d’interface entre les domaines de représentation analogique et numérique des systèmes mixtes de traitement du signal.Il est un élément central en cela que ses performances circonscrivent celles des traitements numériques qui lui succèdent et a fortiori celles de son dispositif hôte. C’est notamment le casdes récepteurs radioélectriques numériques à large bande instantanée. De fait, ces systèmes voient leurs performances de dynamiques instantanées monotonale (DTDR) et bitonale (STDR)– i.e. leur capacité à traiter simultanément des composantes de faible puissance en présence d’une ou plusieurs autres composantes de plus forte puissance – limitées par la linéarité de leur ADC.Ce dernier caractère est quantifié par les performances de dynamique sans raies parasites (SFDR)et distorsion d’intermodulation (IMD) d’un ADC.Les critères de DTDR et de STDR sont essentiels pour les récepteurs radios numériques de guerre électronique conçus pour le traitement des signaux de radiocommunications. En effet, ces dispositifs sont employés à l’établissement de la situation tactique de l’environnement électromagnétique à des fins de support de manoeuvres militaires. La fidélité de la représentation numérique du signal analogique reçu est donc critique. Ainsi, cette thèse vise à étudier la linéarisation des ADC, i.e. l’augmentation des SFDR et IMD, en vue de l’amélioration des dynamiques instantanées de ces récepteurs.Dans ce manuscrit, nous traitons cette problématique selon deux axes différents. Le premier consiste à corriger les distorsions introduites par un ADC au moyen de tables de correspondances(LUT) pré-remplies. À cette fin, nous proposons un algorithme de remplissage de LUT procédant d’une méthode de la littérature par la réduction de moitié du nombre de coefficients à déterminer pour estimer la non-linéarité intégrale (INL) d’un ADC. Sur la base de cette nouvelle méthode,nous développons une approche de correction des non-linéarités dynamiques introduites par un ADC reposant sur une paire de LUT statiques et présentons un exemple d’algorithme permettant de l’opérer. Le second axe du manuscrit repose sur la modélisation comportementale de l’ADC par les séries de Volterra à temps discrets et leurs dérivés. En premier lieu, nous considérons les trois problématiques fondamentales de cette approche de linéarisation : la modélisation ;l’identification de modèle ; et l’inversion de modèle. Puis, nous définissons trois solutions de linéarisation d’ADC aveugles. Enfin, nous analysons l’implémentation sur circuits à réseaux logiques programmables (FPGA) de l’un de ces algorithmes afin d’évaluer la pertinence d’uneopération en temps-réel des échantillons de sortie d’un ADC échantillonnant à une fréquence d’environ 400 MHz. / The analog-to-digital converter (ADC) is a central component of mixed signal systems as the interface between the analog and digital representation spaces. Its performance bounds that of the device it is integrated in. Indeed, ADC linearity is essential for maintaining in the digital space the reliability of its input signal and then that of the information it carries.Wideband digital radio receivers are particularly sensitive to ADC non-linearities. Single-tone and dual-tone dynamic range (respectively STDR and DTDR) of such systems – i.e. the abilityto process simultaneously signal components with high power ratio – are limited by the spurious free dynamic range (SFDR) and intermodulation distortion (IMD) of their internal ADC.DTDR et de STDR are key metrics for electronic warfare wideband digital radio receivers developed for radiocommunication signal processing. As a matter of fact, these equipments are employed for analyzing the tactical situation of the radiofrequency spectrum in order to support military maneuvers. Hence, signal integrity is critical. This thesis deals with the ADC linearization issue in this context. Thus, it aims to study techniques for increasing ADC SFDRand IMD for the purpose of improving dynamic ranges of electronic warfare wideband digitalr eceivers.In this dissertation, the problematic of ADC linearization is approached in two different ways.On the one hand, we consider distortion compensation using pre-filled look-up tables (LUT). Wepropose an algorithm for filling LUTs that stems from an existing method by halving the numberof coefficients required for the integral non-linearity (INL) estimation. Then, based on this new method, we develop an approach for correcting ADC dynamic non-linearities using a couple ofstatic LUTs and we present an example of algorithm for operating this method. On the other hand,we study linearization solutions that rely on behavioural modelling of ADCs using discrete-time Volterra series and its derivatives. First, we address the three fundamental issues of this approach:modelling ; model identification ; and model inversion. Then, we propose three blind linearization algorithms. Finally, we consider the implementation on field programmable gate array (FPGA) of one of them for the purpose of evaluating the relevance of real-time linearization of an ADC sampling at about 400 MHz.

L’ évolution des systèmes radar et de guerre électronique tend à concevoir desrécepteurs numériques possédant des bandes instantanées de plus en plus larges. Cette contraintese reporte sur les Convertisseurs Analogique-Numérique (CAN) qui doivent fournir une fréquenced’échantillonnage de plus en plus élevée tout en conservant une puissance dissipée réduite. Unesolution pour répondre à cette demande est le CAN à Temps Entrelacés (ET-CAN) qui paralléliseM CANs pour augmenter la fréquence d’échantillonnage d’un facteur M tout en restant dansun rapport proportionné avec la puissance dissipée. Cependant, les performances dynamiquesdes ET-CANs sont réduites par des défauts d’entrelacements liés à des différences de processusde fabrication, de leur tension d’alimentation et des variations de température. Ces défautspeuvent être modélisés comme issus des disparités d’offsets, de gains ou décalages temporels etglobalement comme issus des disparités de réponses fréquentielles. Ce sont sur ces dernièresdisparités, moins traitées dans la littérature, que portent nos travaux. L’objectif est d’étudierces disparités pour en déduire un modèle et une méthode d’estimation puis, de proposer desméthodes de compensation numérique qui peuvent être implémentées sur une cible FPGA.Pour cela, nous proposons un modèle général des disparités de réponses fréquentielles desET-CANs pour un nombre de voies M quelconques. Celui-ci mélange une description continuedes disparités et une description discrète de l’entrelacement, résultant sur une expression desdéfauts des ET-CANs comme un filtrage à temps variant périodique (LPTV) du signal analogiqueéchantillonné uniformément. Puis, nous proposons une méthode d’estimation des disparitésdes ET-CANs basée sur les propriétés de corrélation du signal en sortie du modèle, pour Mvoies quelconques. Ensuite, nous définissions une architecture de compensation des disparitésde réponses fréquentielles des ET-CANs et nous étudions ses performances en fonction de sesconfigurations et du signal en entrée. Nous décrivons une implémentation de cette architecturepour M=4 voies entrelacées sur cible FPGA et nous étudions les ressources consommées afin deproposer des pistes d’optimisation. Enfin, nous proposons une seconde méthode de compensationspécifique au cas M=2 voies entrelacées, dérivée de la première mais travaillant sur le signalanalytique en sortie d’un ET-CAN et nous la comparons à une méthode similaire de l’état del’art. / The evolution of radar and electronic warfare systems tends to develop digitalreceivers with wider bandwidths. This constraint reaches the Analog to Digital Converters(ADC) which must provide a sample rate higher and higher while maintaining a reducedpower dissipation. A solution to meet this demand is the Time-Interleaved ADC (TIADC)which parallelizes M ADCs, increasing the sampling frequency of an M factor while still ina proportionate relation to the power loss. However, the dynamic performance of TIADCsare reduced by errors related to the mismatches between the sampling channels, due to themanufacturing processes, the supply voltage and the temperature variations. These errors canbe modeled as the result of offset, gain and clock-skew mismatches and globally as from thefrequency response mismatches. It is these last mismatches, unless addressed in the literaturethat carry our work. The objective is to study these errors to derive a model and an estimationmethod then, to propose digital compensation methods that can be implemented on a FPGAtarget.First, we propose a general TIADC model using frequency response mismatches for any Mchannel number. Our model merge a continuous-time description of mismatches and a discretetimeone of the interleaving process, resulting in an expression of the TIADC errors as a linearperiodic time-varying (LPTV) system applied to the uniformly sampled analog signal. Then,we propose a method to estimate TIADC errors based on the correlation properties of theoutput signal for any M channel. Next, we define a frequency response mismatch compensationarchitecture for TIADC errors and we study its performance related to its configuration and theinput signal. We describe an FPGA implementation of this architecture for M=4 interleavedchannels and we study the resources consumption to propose optimisations. Finally, we proposea second compensation method, specific to M=2 interleaved channels and derived from the firstone, but working on the analytical signal from the TIADC output and we compare it to a similarstate-of-the-art method.

Indiana University-Purdue University Indianapolis (IUPUI) / A novel method of power management and sequential monitoring of several sensors is proposed in this work. Application specific integrated circuits (ASICs) consisting of analog and digital sub-systems forming a system on chip (SoC) has been designed using complementary metal-oxide-semiconductor (CMOS) technology. The analog sub-system comprises the sensor-drivers that convert the input voltage variations to output pulse-frequency. The digital sub-system includes the system management unit (SMU), counter, and shift register modules. This performs the power-usagemanagement, sensor-sequence-control, and output-data-frame-generation functions. The SMU is the key unit within the digital sub-system is that enables or disables a sensor. It captures the pulse waves from a sensor for 3 clocks out of a 16-clock cycle, and transmits the signal to the counter modules. As a result, the analog sub-system is at on-state for only 3/16th fraction (18 %) of the time, leading to reduced power consumption. Three cycles is an optimal number selected for the presented design as the system is unstable with less than 3 cycles and higher clock cycles results in increased power consumption. However, the system can achieve both higher sensitivity and better stability with increased on-state clock cycles. A current-starved-ring-oscillator generates pulse waves that depend on the sensor input parameter. By counting the number of pulses of a sensor-driver in one clock cycle, a sensor input parameter is converted to digital. The digital sub-system constructs a 16-bit frame consisting of 8-bit sensor data, start and stop bits, and a parity bit. Ring oscillators that drive capacitance and resistance-based sensors use an arrangement of delay elements with two levels of control voltages. A bias unit which provides these two levels of control voltages consists of CMOS cascade current mirror to maximize voltage swing for control voltage level swings which give the oscillator wider tuning range and lower temperature induced variations. The ring oscillator was simulated separately for 250 nm and 180 nm CMOS technologies. The simulation results show that when the input voltage of the oscillator is changed by 1 V, the output frequency changes linearly by 440 MHz for 180 nm technology and 206 MHz for 250 nm technology. In a separate design, a temperature sensitive ring oscillator with symmetrical load and temperature dependent input voltage was implemented. When the temperature in the simulation model was varied from -50C to 100C the oscillator output frequency reduced by 510 MHz for the 250 nm and by 810 MHz for 180 nm CMOS technologies, respectively. The presented system does not include memory unit, thus, the captured sensor data has to be instantaneously transmitted to a remote station, e.g. end user interface. This may result in a loss of sensor data in an event of loss of communication link with the remote station. In addition, the presented design does not include transmitter and receiver modules, and thus necessitates the use of separate modules for the transfer of the data.