Ce travail de recherche est basé sur la technologie Ultra Large Bande (ULB), en particulier pour des applications bas débit (standard IEEE 802.15.4) tels que les réseaux de capteurs, les transmissions WPAN ou encore WBAN. La modélisation et la conception d’un récepteur non cohérent ULB pour les communications radio impulsionnelles ont été réalisées. Un des facteurs les plus importants dans les communications ULB est la sensibilité du récepteur, qui détermine la portée de transmission maximale. Un autre facteur aussi important est la consommation d’énergie qui influence directement la durée de vie de la source d’alimentation (batterie). Dans ce contexte, nous présentons dans le chapitre I une introduction sur la technologie ULB et ses diverses applications. Le chapitre II présente la modélisation au niveau système ainsi que d’une étude comparative des récepteurs non cohérents basés sur la détection d’énergie et la pseudo-Détection d’énergie. Dans le chapitre III sont présentés la méthode de conception et de réalisation d’un récepteur non cohérent ULB dans la bande de 3-5 GHz, ainsi que les résultats de mesure et ses performances en termes de sensibilité et de consommation d’énergie. Finalement, le chapitre IV présente une étude théorique sur les différents modes de fonctionnement du transistor MOS afin de mieux comprendre le fonctionnement de chaque bloc du récepteur. Cela permet de proposer de nouvelles architectures pour la détection d’énergie. Enfin, à partir de ces études nous réalisons l’optimisation du récepteur en termes de sensibilité et de consommation d’énergie. / This research is based on Ultra Wide Band (UWB) technology, in particularly for low-Rate applications such as sensor network, WPAN and WBAN (for the standard IEEE 802.15.4). The model and design of a non coherent receiver for UWB impulse radio communications has been completed. One of the most important factors in the UWB communications is the receiver sensitivity which determines the maximum transmission range. Another important factor is the energy consumption that determines the lifetime of the power source (battery). In this context, we present in Chapter I an introduction to UWB technology and its different applications. Chapter II deals with a modeling at the system level of non-Coherent receivers as well as a comparative study based on the energy detection and pseudo energy detection. In Chapter III is presented the method of design and implementation of a non-Coherent UWB receiver in the band of 3-5 GHz, as well as measurement results and performance in terms of sensitivity and power consumption. Finally, Chapter IV presents a theoretical study on the different modes of operation of the MOS transistor to understand the operation of each block of the receiver. This allows us to show the new architectures for energy detection and perform the optimization of receiver in terms of sensitivity and power consumption.

Modern devices such as smartphones and smartwatches spend a large amount of their life idle, waiting for external events. During this time, they are expending energy, using up battery life. Increasing power consumption is a rising concern to users and researchers alike. Power gating, turning off a blocks of hardware when idle, reduces static power consumption. The Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) currently employed in processors leak current. Even in power gated circuits, MOSFET power gating may only save between 60-80% of power. A different type of switch, a Nanoelectromechanical Systems (NEMS) switch, presents an air gap between the source and drain while in the off state, eliminating subthreshold leakage current. The NEMS switch is slower to operate and only has a finite number of switching before breaking. They should be switched with caution. Proposed in this thesis is a hybrid power gating model wherein a MOSFET is placed in series with a NEMS switch. Power gating the Floating Point Unit (FPU) of a processor is studied through the use of modern open source computer architecture simulators. Each switch type is used to model power gating to observe energy savings and performance costs. The hybrid power gating model is more flexible across a variety of applications. Energy savings are comparable to single NEMS switch power gating for applications with low FPU activity. Any performance loss remains low, matching that of MOSFETs. Processor electrical costs are heavily reduced while devices remain operating at a near-optimal speed. / Master of Science / Modern devices such as smartphones and smartwatches spend a large amount of their life idle, waiting for external input. During this time, they are expending energy, using up battery life. The transistors that are inside of them, the minuscule electronics that make these devices work, are not perfect and “leak” current even when not in use. Another type of switch, a mechanical one, has been under development over the last decade. This mechanical switch is slower to operate and is not as reliable as current transistors yet yields a complete disconnection when turned off. Thus, no energy is wasted when a device is sitting idle. While this saves more energy, using a mechanical switch also has the potential to degrade a device’s performance due to its slow operation. In this thesis, the effectiveness of combining the two types of transistors into one process is analyzed. The fast switching times of the currently used transistors can be used in situations where it is difficult to determine whether shutting down a piece of hardware is a good decision. If it has been determined that the circuit may be put to sleep for a long amount of time, the slower but more energy efficient mechanical switch may be used. With this hybrid operation, each transistor is only used in a mode that suits them most appropriately.

Memory unit is one of the fundamental hardware components in system-on-chip (SoC) design, and takes a significant portion of total area cost. Although commercial memory compilers exist, they usually contains memory unit with single-port or dual ports. However, many SoC designs require memory units that support simultaneous multiple reads and writes. They cannot be efficiently generated using the existing memory compilers in the standard cell library. In this thesis, we develop a memory generator that can automatically produce the circuits of multi-port SRAM and all the necessary models required in the standard cell-based design flow. Compared to the design based on dual-port SRAM from memory compilers which usually consists of duplicated copies of SRAM units for supporting multiple write at the same, the proposed design has smaller area cost. Furthermore, we employ various low-power design concepts, including power-gating and adaptive body-bias, to reduce the dynamic and static power of the generated SRAM circuits. Experimental results show that the proposed multi-port SRAM generator can be used to synthesize low-power and low-area register file circuits that support multiple reads and writes at the same time.

Power consumption is one of the most important design factors in modern electronic design. With a large market increase in portable battery-operated devices and push for environmental focus, it is of interest for the industry to decrease the power consumption of modern chips as much as possible. However, as circuits scale down in size the leakage current increases. This increases the static power consumption, and in future technologies the static power is expected to make up most of the overall power consumption. Power gating can decrease static power by isolating a circuit block from the power supply. In large chips, this requires state-retention flip flops and non-volatile memories in order to keep the circuit functioning continuously between power gating sequences. A design concept utilizing this is a Normally Off computer, which is in an off-state with no static power for the majority of the time. This is achieved by using non-volatile logic and memories. This concept has been realized by using a new semiconductor technology developed at Semiconductor Energy Laboratories Corporation Ltd., which is known as crystalline In-Ga-Zn oxide semiconductor material. This technology realizes transistors with an ultra-low off-state current, and enables several novel designs of state-retention circuits suitable for Normally-Off computers. This thesis presents two different architectures of state retention flip flops utilizing In-Ga-Zn oxide semiconductor transistors, which are produced and compared to determine their tradeoffs and effectiveness. These flip flops are then implemented in a 32-bit Normally-Off microprocessor to determine the performance of each implementation. This is evaluated by calculating the energy break-even time, which is the power gating time required to overcome the power overhead introduced by the state-retention flip flops. The resulting circuits and the work in this thesis has been presented at two conferences and submitted for publication in one scientific journal.

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As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in modern low-power microprocessors. This is especially true for ultra-low-voltage (ULV) circuits, where high levels of leakage force designers to chose relatively high threshold voltages, which limits performance. In this thesis, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip. Present power-gating implementations suffer from limitations including non-zero off-state leakage, which can aggregate to a large amount of wasted energy during long idle periods, and high energy overhead, which limits its use to long-term system-wide sleep modes. As this thesis will show however, by vastly increasing the effectiveness of power-gating through the use of emerging technologies, and by implementing aggressive hardware-oriented power-gating policies, leakage in microprocessors can be eliminated to a large extent. This allows the threshold voltage to be lowered, leading to ULV microprocessors with both low switching energy and high performance. The first emerging technology investigated is the Nanoelectromechnical-Systems (NEMS) switch, which is a CMOS-compatible mechanical relay with near-infinite off-resistance and low on-resistance. When used for power-gating, this switch completely eliminates off-state leakage, yet is compact enough to be contained on die. This has tremendous benefits for applications with long sleep times. For example, a NEMS-power-gated architecture performing an FFT per hour consumes 30 times less power than a transistor-power-gated architecture. Additionally, the low on-resistance can lower power-gating area overhead by 36-83\%. The second technology targets the high energy overhead associated with powering a circuit on and off. This thesis demonstrates that a new logic style specifically designed for ULV operation, Sense Amplifier Pass Transistor Logic (SAPTL), requires power-gates that are 8-10 times smaller, and consumes up to 15 times less boot-up energy, compared to static-CMOS. These abilities enable effective power-gating of an SAPTL circuit, even for very short idle periods. Microprocessor simulations demonstrate that a fine-grained power-gating policy, along with this drastically lower overhead, can result in up to a 44\% drop in energy. Encompassing these investigations is an energy estimation framework built around a cycle-accurate microprocessor simulator, which allows a wide range of circuit and power-gating parameters to be optimized. This framework implements two hardware-based power-gating schedulers that are completely invisible to the OS, and have extremely low hardware overhead, allowing for a large number of power-gated regions. All together, this thesis represents the most complete and forward-looking study on power-gating in the ULV region. The results demonstrate that aggressive power-gating allows designers to leverage the very low switching energy of ULV operation, while achieving performance levels that can greatly expand the capabilities of energy-constrained systems. / Ph. D.

Tesis por compendio / Nowadays, thanks to the continuous improvements in the integration scale, more and more cores are added on the same chip, leading to higher system performance. In order to interconnect all nodes, a network-on-chip (NoC) is used, which is in charge of delivering data between cores. However, increasing the number of cores leads to a significant power consumption increase, leading the NoC to be one of the most expensive components in terms of power. Because of this, during the last years, several mechanisms have been proposed to address the NoC power consumption by means of DVFS (Dynamic Voltage and Frequency Scaling) and power-gating strategies. Nevertheless, improvements achieved by these mechanisms are achieved, to a greater or lesser extent, at the cost of system performance, potentially increasing the risk of saturating the network by forming congested points which, in turn, compromise the rest of the system functionality. One side effect is the creation of the "Head-of-Line blocking" effect where congested packets at the head of queues prevent other non-blocked packets from advancing. To address this issue, in this thesis, on one hand, we propose novel congestion control techniques in order to improve system performance by removing the "Head-of-Line" blocking effect. On the other hand, we propose combined solutions adapted to DVFS in order to achieve improvements in terms of performance and power. In addition to this, we propose a path-aware power-gating-based mechanism, which is capable of detecting the flows sharing buffer resources along data paths and perform to switch them off when not needed. With all these combined solutions we can significantly reduce the power consumption of the NoC when compared with state-of-the-art proposals. / Hoy en día, gracias a las mejoras en la escala de integración cada vez se integran más y más núcleos en un mismo chip, mejorando así sus prestaciones. Para interconectar todos los nodos dentro del chip se emplea una red en chip (NoC, Network-on-Chip), la cual es la encargada de intercambiar información entre núcleos. No obstante, aumentar el número de núcleos en el chip también conlleva a su vez un importante incremento en el consumo de la NoC, haciendo que ésta se convierta en una de las partes más caras del chip en términos de consumo. Por ello, en los últimos años se han propuesto diversas técnicas de ahorro de energía orientadas a reducir el consumo de la NoC mediante el uso de DVFS (Dynamic Voltage and Frequency Scaling) o estrategias basadas en "power-gating". Sin embargo, éstas mejoras de consumo normalmente se obtienen a costa de sacrificar, en mayor o menor medida, las prestaciones del sistema, aumentado potencialmente así el riesgo de saturar la red, generando puntos de congestión que, a su vez, comprometen el rendimiento del resto del sistema. Un efecto colateral es el "Head-of-Line blocking", mediante el que paquetes congestionados en la cabeza de la cola impiden que otros paquetes no congestionados avancen. Con el fin de solucionar este problema, en ésta tesis, en primer lugar, proponemos técnicas novedosas de control de congestión para incrementar el rendimiento del sistema mediante la eliminación del "Head-of-Line blocking", mientras que, por otra parte, proponemos soluciones combinadas adaptadas a DVFS con el fin de conseguir mejoras en términos de rendimiento y energía. Además, proponemos una técnica de "power-gating" orientada a rutas de datos, la cual es capaz de detectar flujos de datos compartiendo recursos a lo largo de rutas y apagar dichos recursos de forma dinámica cuando no son necesarios. Con todas éstas soluciones combinadas podemos reducir el consumo de energía de la NoC en comparación con otras técnicas presentes en el estado del arte. / Hui en dia, gr\`acies a les millores en l'escala d'integraci\'o, cada vegada s'integren m\'es i m\'es nuclis en un mateix xip, la qual cosa millora les seues prestacions. Per tal d'interconectar tots els nodes dins el xip es fa \'us d'una Xarxa en Xip (NoC; Network-on-Chip), la qual \'es l'encarregada d'intercanviar informaci\'o entre els nuclis. No obstant aix\`o, incrementar el nombre de nuclis en el xip tamb\'e comporta un important augment en el consum de la NoC, la qual cosa fa que aquesta es convertisca en una de les parts m\'es costoses del xip en termes de consum. Per aix\`o, en els \'ultims anys s'han proposat diverses t\`ecniques d'estalvi d'energia orientades a reduir el consum de la NoC mitjançant l'\'us de DVFS (Dynamic Voltage and Frequency Scaling) o estrat\`egies basades en ``power-gating''. Malgrat aix\`o, aquestes millores en les prestacions normalment s'obtenen a costa de sacrificar, en major o menor mesura, les prestacions del sistema i augmenta aix\'i el risc de saturar la xarxa al generar-se punts de congesti\'o, que al mateix temps, comprometen el rendiment de la resta del sistema. Un efecte col-lateral \'es el ``Head-of- Line blocking'', mitjançant el qual, els paquets congestionats al cap de la cua, impedixen que altres paquets no congestionats avancen. A fi de solucionar eixe problema, en aquesta tesi, en primer lloc, proposem noves t\`ecniques de control de congesti\'o amb l'objectiu d'incrementar el rendiment del sistema per mitj\`a de l'eliminaci\'o del ``Head-of- Line blocking'', i d'altra banda, proposem solucions combinades adaptades a DVFS amb la finalitat d'aconseguir millores en termes de rendiment i energia. A m\'es, proposem una t\`ecnica de ``power-gating'' orientada a rutes de dades, la qual \'es capa\c c de detectar fluxos de dades al compartir recursos al llarg de les rutes i apagar eixos recursos de forma din\`amica quan no s\'on necessaris. Amb totes aquestes solucions combinades podem reduir el consum d'energia de la NoC en comparaci\'o amb altres t\`ecniques presents en l'estat de l'art. / Escamilla López, JV. (2017). Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/90419 / Compendio

Les systèmes intégrés sont aujourd’hui de plus en plus fréquemment confrontés à des contraintes de faible consommation ou d’efficacité énergétique. Ces problématiques se doivent d’être intégrées le plus en amont possible dans le flot de conception afin de réduire les temps de design et d’éviter de nombreuses itérations dans le flot. Dans ce contexte, le projet collaboratif HiCool, partenariat entre les laboratoires LIRMM et TIMA, les sociétés Defacto, Docea et ST Microelectronics, a mis en place une stratégie et un flot de conception pour concevoir des systèmes intégrés faible consommation tout en facilitant la réutilisation de blocks matériels (IPs) existants. L’approche proposée dans cette thèse s’intègre dans cette stratégie en apportant une petite dose d’asynchronisme dans des systèmes complètement synchrones. En effet, la réduction de la consommation est basée sur le constat que l’activation permanente de la totalité du circuit est inutile dans bien des cas. Néanmoins, contrôler l’activité avec des techniques de « clock gating » ou de « power gating » nécessitent usuellement d’effectuer un re-design du système et d’ajouter un organe de commande pour contrôler l’activation des zones effectuant un traitement. Le travail présenté dans ce manuscrit définit une stratégie basée sur des contrôleurs d’horloge et de domaine d’alimentation, asynchrones, distribués et facilement insérables dans un circuit avec un coût de re-design des plus réduit. / Today integrated systems are increasingly faced with the constraints of low consumption or energy efficiency. These issues need to be integrated as far upstream as possible in the design flow to reduce design time and avoid much iteration in the flow. In this context, the collaborative project HiCool, between LIRMM and TIMA laboratories, Defacto, Docea and ST Microelectronics companies, has set up a strategy and design flow to design integrated low power systems while facilitating the reuse of existing hardware blocks (IPs). The approach proposed in this thesis fits into this strategy by bringing a small dose of asynchrony in completely synchronous systems. Indeed, the reduction in consumption is based on the observation that permanent activation of the entire circuit is unnecessary in many cases. However, controlling the activity with techniques of "clock gating" or "power gating" usually need to perform a re-design of the system and to add a control device for controlling activation of areas effecting treatment. The work presented in this manuscript provides a strategy based clock controllers and power domain, asynchronous, distributed and easily insertable into a circuit with a low cost design.

L’engouement actuel pour les applications de type réseaux de capteurs sans-fil ou internet des objets (IoT) relance la nécessité, alors initiée par les applications mobiles, de concevoir des émetteurs-récepteurs radio à basse consommation. Dans ce contexte, l’objet des travaux de thèse est de proposer des techniques de réduction de la consommation des récepteurs radio tout en minimisant l’impact sur leur architecture de manière à pouvoir adapter leur consommation aux besoins de performance.Pour ce faire, l’utilisation intermittente du convertisseur analogique numérique (ADC) a, dans un premier temps, été étudiée puis celle-ci a été généralisée à l’ensemble du récepteur. Pour chacune de ces approches, une modélisation de la dégradation des performances en termes de taux d’erreur (BER) a été confrontée à une estimation de la réduction de la consommation engendrée. Par ailleurs, l’impact de l’ajout de modules spécifiques aux techniques proposées est décrit à l’aide de résultats concernant leurs complexités et leurs consommations. L’ensemble de ces résultats s’inscrit pleinement dans le domaine de recherche des récepteurs adaptatifs pour lesquels les performances sont adaptées au canal de transmission en temps réel.Finalement, une technique de compensation digitale des défauts de quadrature a été proposée, rendant possible l’utilisation d’une PLL moins énergivore mais avec des performances dégradées. Cette technique utilise une recherche par dichotomie des poids de compensation des défauts de quadrature, lui permettant de converger suffisamment rapidement pour pouvoir réaliser la compensation sur une portion connue du message reçu et ainsi éviter une perte d’information. / The recent craze for the Wireless Sensor Networks (WSN) and the Internet of Things (IoT) applications boosts the necessity, previously introduced by the mobile applications, to design low power transceivers. In this context, the purpose of this thesis is to propose some techniques to reduce the power consumption of RF receivers while minimizing the impact on their architecture in order to be able to adapt their power consumption to the required performances.To do so, the study of the intermittent use of the analog-to-digital converter (ADC) is firstly proposed and then extended to the whole receiver. In each case, the degradation of the receiver performances in terms of bit error rate (BER) is compared to an estimate of the obtained decrease of the power consumption. Moreover, the complexity and the overhead power consumption of the modules involved in the processing of the proposed techniques are also estimated and discussed. All these results are part of the field of research called “adaptive receiver” that tries to adapt the receiver performances to its environment in real time.Finally, a digital compensation technique of the quadrature imbalances was proposed. It allows using a less energy-consuming PLL but with degraded quadrature performances and compensating the mismatches in the digital domain. This technique uses a dichotomic search of the compensation weights allowing a fast convergence in order for the compensation to be done during the reception of a known portion of the received message and therefore avoiding a loss of information.

Power supply noise has become a critical issue for low power and high performance circuit design in recent years. The rapid scaling of the CMOS process has pushed the limit further and further in building low-cost and increasingly complex digital VLSI systems. Continued technology scaling has contributed to significant improvements in performance, increases in transistor density, and reductions in power consumption. However, smaller feature sizes, higher operation frequencies, and supply voltage reduction make current and future VLSI systems more vulnerable to power supply noise. Therefore, there is a strong demand for strategies to prevent problems caused by power supply noise. Design challenges exist in different design phases to reduce power supply noise. In terms of physical design, careful power distribution design is required, since it directly determines the quality of power stability and the timing integrity. In addition, power management, such as switching mode of the power gating technique, is another major challenge during the circuit design phase. A bad power gating switching strategy may draw an excessive rush current and slow down other active circuitry. After the circuit is implemented, another critical design challenge is to estimate power supply noise. Designers need to be aware of the voltage drop in order to enhance the power distribution network without wasting unnecessary design resources. However, estimating power supply noise is usually difficult, especially finding the circuit activity which induces the maximum supply noise. Blind search may be very time consuming and not effective. At post-silicon test, detecting power supply noise within a chip is also challenging. The visibility of supply noise is low since there is no trivial method to measure it. However, the supply noise measurement result on silicon is critical to debug and to characterize the chip. This dissertation focuses on novel circuit designs and design methodologies to prevent problems resulted from power supply noise in different design phases. First, a supply noise estimation methodology is developed. This methodology systematically searches the circuit activity inducing the maximum voltage drop. Meanwhile, once the circuit activity is found, it is validated through instruction execution. Therefore, the estimated voltage drop is a realistic estimation close to the real phenomenon. Simulation results show that this technique is able to find the circuit activity more efficiently and effectively compared to random simulation. Second, two on-chip power supply noise detectors are designed to improve the visibility of voltage drop during test phase. The first detector facilitates insertion of numerous detectors when there is a need for additional test points, such as a fine-grained power gating design or a circuit with multiple power domains. It focuses on minimizing the area consumption of the existing detector. This detector significantly reduces the area consumption compared to the conventional approach without losing accuracy due to the area minimization. The major goal of designing the second on-chip detector is to achieve self-calibration under process and temperature variations. Simulation and silicon measurement results demonstrate the capability of self-calibration regardless these variations. Lastly, a robust power gating reactivation technique is designed. This reactivation scheme utilizes the on-chip detector presented in this dissertation to monitor power supply noise in real time. It takes a dynamic approach to control the wakeup sequence according to the ambient voltage level. Simulation results demonstrate the ability to prevent the excessive voltage drop while the ambient active circuitry induces a high voltage drop during the wakeup phase. As a result, the fixed design resource, which is used to prevent the voltage emergency, can potentially be reduced by utilizing the dynamic reactivation scheme. / text