The purpose of this study was to develop, digitally record, evaluate, and equate Cantonese trisyllabic words which could then be used in the measurement of the speech reception threshold. A selection of 90 frequently utilized trisyllabic words were selected and then digitally recorded by male and female talkers of Standard Cantonese and presented to 20 subjects with normal hearing beginning at 6 dB below their pure-tone average (PTA) and ascending in 2 dB increments until one of the following criteria had been met: (a) the participant responded correctly to 100% of the test items, or (b) the presentation level reached 16 dB HL. Using logistic regression, psychometric functions were calculated for each word. Twenty-eight trisyllabic words with the steepest psychometric function slopes were selected. The psychometric function slopes for the 28 selected words, at 50% threshold, ranged from 10.3 %/dB to 19.6 %/dB (M = 14.5 %/dB) for the male talker and from 10.3 %/dB to 22.7 %/dB (M = 14.9 %/dB) for the female talker. To decrease the variability among the words the intensities were digitally adjusted to match the mean subject PTA (4.5 dB HL). The resulting lists included mean slopes from 20 to 80% with of a range of 8.9 %/dB to 16.9 %/dB (M = 12.6 %/dB) for the male talker and a range of 8.9 %/dB to 19.7 %/dB (M = 12.9 %/dB) for the female talker. Digital recordings of the psychometrically equivalent trisyllabic words are available on compact disc.

No description available.

This thesis aims to explore the current situation, challenges, and proposed recommendation of digitally-disadvantaged languages (DDL) in the social and digital context from six stakeholders' perspectives: academia, civil society organizations, for-profit corporations, government, language community, and language supporters, with additional language policy analysis in Indonesia and Sweden. Three interrelated theories - the digital divide, ecolinguistics, and digital justice - provide a framework for understanding digitally-disadvantaged languages' situations and challenges. The thesis employs semi-structured interviews for data collection and thematic analysis to analyze the collected data, and a comparative policy analysis accompanies it on digital language regulation in Indonesia and Sweden. Two established frameworks on general digital development issues, Principles for Digital Development (PDD) and Digital Justice Principles (DJP), were introduced to compare these languages’ challenges and propose recommendations for their future. Although the comparison demonstrates a strong connection between these established principles and these languages, there is still a need for a tailored framework focused explicitly on digitally-disadvantaged languages. The thesis concludes with the final result: collaborative efforts among stakeholders, especially the language community as the central actor and the government as the regulator, are the key to improving digital support and accommodating the need for digitally-disadvantaged languages.

No description available.

Le projet HODISS dans le cadre duquel s'effectue nos travaux adresse la problématique de la synchronisation globale des systèmes complexes sur puce (System-on-Chip ou SOCs, par exemple un multiprocesseur monolithique). Les approches classiques de distribution d'horloges étant devenues de plus en plus obsolètes à cause de l'augmentation de la fréquence d'horloge, l'accroissement des temps de propagation, l'accroissement de la complexité des circuits et les incertitudes de fabrication, les concepteurs s’intéressent (pour contourner ces difficultés) à d'autres techniques basées entre autres sur les oscillateurs distribués. La difficulté majeure de cette dernière approche réside dans la capacité d’assurer le synchronisme global du système. Nous proposons un système d'horlogerie distribuée basé sur un réseau d’oscillateurs couplés en phase. Pour synchroniser ces oscillateurs, chacun d'eux est en fait une boucle à verrouillage de phase qui permet ainsi d'assurer un couplage en phase avec les oscillateurs des zones voisines. Nous analysons la stabilité de l'état synchrone dans des réseaux cartésiens identiques de boucles à verrouillage de phase entièrement numériques (ADPLLs). Sous certaines conditions, on montre que l'ensemble du réseau peut synchroniser à la fois en phase et en fréquence. Un aspect majeur de cette étude réside dans le fait que, en l'absence d'une horloge de référence absolue, le filtre de boucle dans chaque ADPLL est piloté par les fronts montants irréguliers de l'oscillateur local et, par conséquent, n'est pas régi par les mêmes équations d'état selon que l'horloge locale est avancée ou retardée par rapport au signal considéré comme référence. Sous des hypothèses simples, ces réseaux d'ADPLLs dits "auto-échantillonnés" peuvent être décrits comme des systèmes linéaires par morceaux dont la stabilité est notoirement difficile à établir. L'une des principales contributions que nous présentons est la définition de règles de conception simples qui doivent être satisfaites sur les coefficients de chaque filtre de boucle afin d'obtenir une synchronisation dans un réseau cartésien de taille quelconque. Les simulations transitoires indiquent que cette condition nécessaire de synchronisation peut également être suffisante pour une classe particulière d'ADPLLs "auto-échantillonnés". / The HODISS project, context in which this work is achieved, addresses the problem of global synchronization of complex systems-on-chip (SOCs, such as a monolithic multiprocessor). Since the traditional approaches of clock distribution are less used due to the increase of the clock frequency, increased delay, increased circuit complexity and uncertainties of manufacture, designers are interested (to circumvent these difficulties) to other techniques based among others on distributed synchronous clocks. The main difficulty of this latter approach is the ability to ensure the overall system synchronization. We propose a clock distribution system based on a network of phase-coupled oscillators. To synchronize these oscillators, each is in fact a phase-locked loop which allows to ensure a phase coupling with the nearest neighboring oscillators. We analyze the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs). Under certain conditions, we show that the entire network may synchronize both in phase and frequency. A key aspect of this study lies in the fact that, in the absence of an absolute reference clock, the loop-filter in each ADPLL is operated on the irregular rising edges of the local oscillator and consequently, does not use the same operands depending on whether the local clock is leading or lagging with respect to the signal considered as reference. Under simple assumptions, these networks of so-called “self-sampled” all-digital phase-locked-loops (SS-ADPLLs) can be described as piecewise-linear systems, the stability of which is notoriously difficult to establish. One of the main contributions presented here is the definition of simple design rules that must be satisfied by the coefficients of each loop-filter in order to achieve synchronization in a Cartesian network of arbitrary size. Transient simulations indicate that this necessary synchronization condition may also be sufficient for a specific class of SS-ADPLLs.

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.

Innovation in wireless communication has resulted in accelerating demand for smartphones using multiple communications protocols such as WiFi, Bluetooth and the many cellular standards deployed around the world. The variety of frequency, bandwidth and power requirements associated with each standard typically calls for the implementation of separate radio frequency (RF) front end hardware for each standard. This is a less-than-ideal solution in terms of cost and device area. Software-defined radio (SDR) promises to solve this problem by allowing the RF hardware to be digitally reconfigurable to adapt to any wireless standard. The application of machine learning and cognition algorithms to SDR will enable cognitive radios and cognitive wireless networks, which will be able to intelligently adapt to user needs and surrounding radio spectrum conditions. The challenge of fully reconfigurable transceivers is in implementing digitally-controlled RF circuits which have comparable performance to their fixed-frequency counterparts. Switching-mode power amplifiers (SMPA) are likely to be an important part of fully reconfigurable transmitters since their switching operation provides inherent compatibility with digital circuits, with the added benefit of very high efficiency. As a step to understanding the RF requirements of high efficiency and switching PAs, an inverse class F PA in push-pull configuration is implemented. This configuration is chosen for its similarity to the current mode class D (CMCD) topology. The fabricated PA achieves a peak drain efficiency of over 75% with 42.7 dBm (18.6 W) output power at 2.46 GHz. Since SMPAs cannot directly provide the linearity required by current and future wireless communications standards, amplitude information must be encoded into the RF signal in a different way. Given the superior time resolution of digital integrated circuit (IC) technology, a logical solution is to encode this information into the timing of the signal. The two most common techniques for doing so are pulse width modulation and delta-sigma modulation. However, the design of delta-sigma modulators requires simulation as part of the design process due to the lack of closed-form relationships between modulator parameters (such as resolution and oversampling) and performance figures (such as coding efficiency and signal quality). In particular, the coding efficiency is often ignored although it is an important part of ensuring transmitter efficiency with respect to the desired signal. A study of these relationships is carried out to observe the tradeoffs between them. It is found that increasing the speed or complexity of a DS modulated system does not necessarily translate to performance benefits as one might expect. These observations can have a strong impact on design choices at the system level.

This master´s thesis deals an active elements called digitally controlled current amplifier, multiple-output current follower and its usage in frequency filters. These frequency filters operate in a pure current mode. In the first part of this work are presented the different types of current active elements. Multiple-output current follower, digitally controlled current amplifier (MO-CF, DCCA). In the second part of this work are introduced particular methods of design tunable frequency filters. Special attention is given to using the design method of via autonomous circuits because it is one of the most. In the last part of this thesis are designed and computer-simulated individual multifunction tunable frequency filters with those already active yet elements. These filters were designed via autonomous circuits or modification of existing circuits. The functionality of the proposed filtres have been verified by computer simulation. Snap3 program was used for the symbolic analyse of circuit and OrCad PSpice program was used to simulate the characteristics of multifunction filters.

This master´s thesis deals an active elements called digitally controlled current amplifier, multiple-output current follower and its usage in tunable frequency filters. These tunable frequency filters operate in a pure current mode. In the first part of this work are presented the different types of current active elements. Universal current conveyor, multiple-output current follower, digitally controlled current amplifier (UCC, MO-CF, DCCA). In the second part of this work are introduced particular methods of design tunable frequency filters. Special attention is given to using the design method of via autonomous circuits because it is one of the most. In the last part of this thesis are designed and computer-simulated individual multifunction tunable frequency filters with those already active yet elements. These filters were designed via autonomous circuits or modification of existing circuits. The functionality of the proposed filtres have been verified by computer simulation. Snap3 program was used for the symbolic analyse of circuit and OrCad PSpice program was used to simulate the characteristics of multifunction filters.

This master´s thesis is about MO-CF, DCCA and CC frequency filters with current active elements proposal. Current active elements, their features, structure and utilization are shown in introduction. A progress propose of universal filter is described in thesis. With the use of active elements has been established an universal filter with basic parameter changes capability (quality and limit frequency). SNAP software was used in this propose and the characteristics simulation have been done in OrCad-PSpice. For control changes of quality and limit frequency was used active element DCCA. The main circuit board of universal controlled filter was made with the EAGLE software. Created sample was measured for each type of filter, the different quality and limit frequency. These values were compared with simulated values of the filter.