International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / The monitoring of multi phase 400 Hz aircraft power includes monitoring the phase voltages, currents, real powers, and frequency. This paper describes the design of a multi channel card that uses digital signal processing (DSP) to measure these parameters on a cycle by cycle basis. The card measures the average, peak, minimum cycle, and maximum cycle values of these parameters.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / A DSP modem is often designed as a set of processing blocks that replace the corresponding blocks of an analog prototype. Such a design is sub-optimal, inheriting legacy compromises made in the analog design while discarding important design options unique to the DSP domain. In part I of this two part paper, we used multirate processing to transform a digital down converter from an emulation of the standard analog architecture to a DSP based solution that reversed the order of frequency selection, filtering, and resampling. We continue this tack of embedding traditional processing tasks into multirate DSP solutions that perform multiple simultaneous processing tasks.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / Digital signal processing has inexorably been woven into the fabric of every function performed in a modern radio communication system. In the rush to the marketplace, we have fielded many DSP designs based on analog prototype solutions containing legacy compromises appropriate for the technology of a time past. As we design the next generation radio we pause to examine and review past solutions to past radio problems. In this review we discover a number of DSP design methods and perspectives that lead to cost and performance advantages for use in the next generation radio.

ITC/USA 2011 Conference Proceedings / The Forty-Seventh Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2011 / Bally's Las Vegas, Las Vegas, Nevada / Commercial off-the-shelf (COTS) graphics processing units (GPU) perform the signal processing operations needed for video games and similar consumer applications. The high volume and competitive nature of that industry have produced inexpensive GPUs with impressive amounts of signal processing power. These devices use parallel processing architectures to execute DSP algorithms far faster than single, or even multi-core central processing units typically found in workstations. This paper describes a project which improves the performance of a radar telemetry application using the NVidia™ brand GPU and CUDA™ software, although the results could be extended to other devices.

ITC/USA 2011 Conference Proceedings / The Forty-Seventh Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2011 / Bally's Las Vegas, Las Vegas, Nevada / This paper describes the design of an inexpensive and scalable transmitter for a Multiple-Input Multiple-Output (MIMO) communication system. The transmitter is intended to be used in aerospace applications, especially in spin stabilized vehicles. A field programmable gate array (FPGA) in the modulator will implement a modified Alamouti space time block code which will take advantage of the cyclostationary nature of the channel to increase the system data rate.

This research project proposed a unique solution to make use of these base stations to keep all subscribers alerted with warning of possible disaster should that be required. As the current, network does not provide a provision for such a noble approach, a new network model has been developed and simulated to interface a sensor (weather station, WeS), with WiMAX weather station. The weather station is based on DSP processor to receive a digitised sensor values, process these values, analyse them and if they fall within the alert zones, packet them according to WiMAX protocol and send them to subscribers. The developed standard bypasses any commercial network to offer free transmission to subscribers. This setup is also able to extract information on weather condition or react on uncertainty, i.e. disaster scenarios. Natural disasters, such as torrent, tornado/ hurricane, volcano eruption, earthquake, Tsunamis or landslide are increasing. Unfortunately they bring with them human tragedies, environment catastrophes, villages, cities and counties are subject to endless devastation during and after the destructive forces. Water, electricity and gas supply are most disrupted and difficult to restore in short time. However, communication is another item that can be affected adversely but WLAN with specific considerations, should be excluded from the effect. This project presents a solution, albeit minor relative to the maximum effect of the disaster, but will keep the telecommunication/communication in operation. Our novel technique, a “Clone Wireless Wide Area Network (CloneWAN)” is a clone wireless network to the wired Network. In the event of natural calamities, it gives continuity of network operation. It is based on WiMAX. The realization of CloneWAN has been formed and simulated to set the national network of the UAE at its correct form. CloneWAN model has been simulated with Opnet platform. All results revealed that the model is complete. The interface to Alerting System is discussed. Results show that the dynamic behavior of the parameters delay and Throughput of CloneWAN model is stable over various and different load scenarios. WiMAX is a de-facto standard in the current and future network requirement standards. Its main component is the Base Station which is normally stationed in the air, high enough to couple signals from other base stations. It is purpose is merely focused on networking signals for commercial purposes. The suggested hardware interface for the Weather Station is based on DSP SHARC processor. The model has been written in C and simulated under Opnet package. A number of scenarios have been set to represent different disasters worldwide. All results are listed and discussed later in the thesis.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / In this paper, a new concept in PCM telemetry encoding equipment is described. Existing "programmable" PCM encoders allow only simple changes in the functionality of the hardware, such as input gain, offset, and word formatting. More importantly, these encoders do not provide capability for "in-flight" processing of signals and in general have not taken advantage of existing hardware and software digital signal processing technology. In-flight processing of signals can provide a significant reduction in the required transmission bandwidth, allowing additional data that may not have otherwise been transmitted to be sent on the telemetry channel. A modular digital signal processor (DSP) based PCM encoder architecture is described that has a set of on-board processing algorithms configurable via a simple-to-use graphical user interface. Algorithms included are compression (lossy and lossless), Fourier transforms of various resolutions (typically followed by peak detection to provide a data rate reduction), extreme values (max, min, rms), time filtering, regression, trajectory prediction, and serial data stream processing. Custom algorithms can be developed and included as part of the suite of processing algorithms. The preprocessing algorithms exist as firmware on the DSPs and can accommodate as many different signals as the processing bandwidth of the DSP can handle. Typically one DSP can handle many input signals and different algorithms. The encoder is programmable via a standard RS-232 serial interface allowing the signal input configuration, telemetry frame layout, and on-board processing algorithms to be changed quickly.

Ingeniero Civil Electricista / En el actual escenario mundial, donde cada vez es más frecuente que pequeños generadores ERNC suministren energ ía el éctrica residencial, comercial e inclusive industrial, se prevee que los sistemas de el éctricos de potencia tradicionales migren a sistemas que incorporen pequeños generadores ERNC inyectando su energí a excedente directamente a la red de distribución. Frente a este nuevo escenario, el Estado ha tenido que legislar al respecto promulgando una ley que regula el ingreso de estas nuevas tecnologí as y desarrollando el reglamento correspondiente con la finalidad de hacer sustentanble y mantener de forma segura los sistemas eléctricos de potencia, exigíendolos cumplir con normas técnicas. Además la nueva legislación incentiva el ingreso de estos nuevos actores con el pago, de las empresas distribuidoras de la energía excedente inyectada. Para poder incorporar estos pequeños generadores dentro del sistema eléctrico, se propone la construcción de un dispositivo que amplí e la forma de operación de distintos tipos de estos pequeños generadores, y que además permita que estos cumplan con las nuevas normativas para que se incorporen al sistema eléctrico de distribución y sincronizarlos en forma segura. El objetivo del trabajo de título es desarrollar y construir un dispositivo, que cumpla la función de interfaz entre el generador y consumo-red, con una potencia de 10[kW], que sea autónomo y que permita operar con un consumo aislado o sincronizado, que busca obtener un mejor rendimiento uniendo fases para el caso de operación en isla con conexión monofásica, y además, evaluar la rentabilidad del dispositivo. Se contruye un conversor de 7 piernas que se compone principalmente de un DSP que controla su funcionamiento, placas de transductores que miden variables eléctricas necesarias para el control y la placa del conversor, la cual recibe las señales de control y controla los circuitos de potencia. Se acondiciona parte del laboratorio de electrónica de potencia para realizar pruebas controladas y seguras. Se diseñan los algoritmos de modulación y control del sistema, que corresponden a modulación de espacio vectorial en 3 dimensiones que permite tener una salida del inversor trifásica con neutro, lo que permite conectar carga directamente, y control resonante que tiene la característica de controlar en torno a una frecuencia específica de 50[Hz]. Se realizan las pruebas de algoritmos y se registran las salidas que verifica que el inversor mantiene una tensión de salida a 50[Hz], en vacío, con variación de carga e igualando fases. Se calcula una breve evaluación económica para estimar la rentabilidad del equipo. Finalmente se obtiene un dispositivo experimental que puede servir como referencia de diseño y construcción de un conversor, desarrollo de algoritmos de modulación y control. Además de una base de aprendizaje en uso software para programar DSP y hardware de electr onica de potencia.

Applications run on embedded processors are constantly evolving. They are for the most part growing more complex and the processors have to increase their performance to keep up. In this thesis, an embedded DSP SIMT processor with decoupled execution units is under investigation. A SIMT processor exploits the parallelism gained from issuing instructions to functional units or to decoupled execution units. In its basic form only a single instruction is issued per cycle. If the control of the decoupled execution units become too fine-grained or if the control burden of the master core becomes sufficiently high, the fetching and decoding of instructions can become a bottleneck of the system. This thesis investigates how to parallelize the instruction fetch, decode and issue process. Traditional parallel fetch and decode methods in superscalar and VLIW architectures are investigated. Benefits and drawbacks of the two are presented and discussed. One superscalar design and one VLIW design are implemented in RTL, and their costs and performances are compared using a benchmark program and synthesis. It is found that both the superscalar and the VLIW designs outperform a baseline scalar processor as expected, with the VLIW design performing slightly better than the superscalar design. The VLIW design is found to be able to achieve a higher clock frequency, with an area comparable to the area of the superscalar design. This thesis also investigates how instructions can be encoded to lower the decode complexity and increase the speed of issue to decoupled execution units. A number of possible encodings are proposed and discussed. Simulations show that the encodings have a possibility to considerably lower the time spent issuing to decoupled execution units.

Data streaming applications, such as signal processing, multimedia applications, often require high computing capacity, yet also have stringent power constraints, especially in portable devices. General purpose processors can no longer meet these requirements due to their sequential software execution. Although fixed logic ASICs are usually able to achieve the best performance and energy efficiency, ASIC solutions are expensive to design and their lack of flexibility makes them unable to accommodate functional changes or new system requirements. Reconfigurable systems have long been proposed to bridge the gap between the flexibility of software processors and performance of hardware circuits. Unfortunately, mainstream reconfigurable FPGA designs suffer from high cost of area, power consumption and speed due to the routing area overhead and timing penalty of their bit-level fine granularity. In this dissertation, we present an architecture design, application mapping and performance evaluation of a novel coarse-grained reconfigurable architecture, named SmartCell, for data streaming applications. The system tiles a large number of computing cell units in a 2D mesh structure, with four coarse-grained processing elements developed inside each cell to form a quad structure. Based on this structure, a hierarchical reconfigurable network is developed to provide flexible on-chip communication among computing resources: including fully connected crossbar, nearest neighbor connection and clustered mesh network. SmartCell can be configured to operate in various computing modes, including SIMD, MIMD and systolic array styles to fit for different application requirements. The coarse-grained SmartCell has the potential to improve the power and energy efficiency compared with fine-grained FPGAs. It is also able to provide high performance comparable to the fixed function ASICs through deep pipelining and large amount of computing parallelism. Dynamic reconfiguration is also addressed in this dissertation. To evaluate its performance, a set of benchmark applications has been successfully mapped onto the SmartCell system, ranging from signal processing, multimedia applications to scientific computing and data encryption. A 4 by 4 SmartCell prototype system was initially designed in CMOS standard cell ASIC with 130 nm process. The chip occupies 8.2 mm square and dissipates 1.6 mW/MHz under fully operation. The results show that the SmartCell can bridge the performance and flexibility gap between logic specific ASICs and reconfigurable FPGAs. SmartCell is also about 8% and 69% more energy efficient and achieves 4x and 2x throughput gains compared with Montium and RaPiD CGRAs. Based on our first SmartCell prototype experiences, an improved SmartCell-II architecture was developed, which includes distributed data memory, segmented instruction format and improved dynamic configuration schemes. A novel parallel FFT algorithm with balanced workloads and optimized data flow was also proposed and successfully mapped onto SmartCell-II for performance evaluations. A 4 by 4 SmartCell-II prototype was then synthesized into standard cell ASICs with 90 nm process. The results show that SmartCell-II consists of 2.0 million gates and is fully functional at up to 295 MHz with 3.1 mW/MHz power consumption. SmartCell-II is about 3.6 and 28.9 times more energy efficient than Xilinx FPGA and TI's high performance DSPs, respectively. It is concluded that the SmartCell is able to provide a promising solution to achieve high performance and energy efficiency for future data streaming applications.