It is clear that Cryptography is computationally intensive. It is also known that embedded systems have slow clock rates and less memory. The idea for this thesis was to study the possibilities for analysis of cryptography on embedded systems. The basic approach was the implementation of cryptographic algorithms on high-end, state-of-the-art, DSP chips in order to study the various parameters that optimize the performance of the chip while keeping the overhead of encryption and decryption to a minimum. Embedded systems are very resource sensitive. An embedded system is composed of different components, which are implemented in both hardware and software. Therefore, hardware-software co-synthesis is a crucial factor affecting the performance of embedded systems. Encryption algorithms are generally classified as data-dominated systems rather than ubiquitous control-dominated systems. Data-dominated systems have a high degree of parallelism. Embedded systems populate the new generation gadgets such as cell phones and Smartcards where the encryption algorithms are obviously an integral part of the system. Due to the proliferation of embedded systems in all the current areas, there is a need for the systematic study of encryption techniques from the embedded systems point of view. This thesis explored the different ways encryption algorithms can be made to run faster with much less memory. Some of the issues investigated were overlapped scheduling techniques for high-level synthesis, structural partitioning, real-time issues, reusability and functionality, random number and unique key generators, seamless integration of cryptographic code with other applications and architecture specific optimization techniques.

Modern high-performance digital signal processing (DSP) applications face constantly increasing performance requirements and are becoming increasingly challenging to develop and work with. In DSP paradigm, many researchers see potential in achieving algorithm speed-up by employing Field Programmable Gate Arrays (FPGAs) – reconfigurable hardware with parallelism feature. However, developing applications for FPGAs incur particular challenges on the development flow. This work proposes a scalable hybrid DSP system for performing high-performance signal processing applications. The system employs hybrid CPU + FPGA architecture of commercially available, off-the-shelf (COTS) FPGAs and central processing units (CPU) of personal computers. In this work an example implementation of a multi-channel cross-correlator is investigated and delivered using a new development paradigm. The correlator is implemented on the XD1000 development system using a high-level FPGA programming tool – Impulse CoDeveloper. Analysis of DSP application development in a hybrid CPU+FPGA system employing the high-level programming tool Impulse C is presented. Potential of the selected tool to deliver algorithm speed-ups is investigated using reference multi-channel correlator software. Particular attention is devoted to input/output (I/O) implementation, which is considered one of the most challenging problems in FPGA design development. This work delivers an I/O framework based on PCI Express interface for the proposed high-performance scalable DSP system. Using Stratix II GX PCI Express Development Board from Altera Corporation, a scalable and flexible communication approach for the multi-channel correlator is delivered. This framework can be adapted to perform other high-performance streaming DSP applications. The outcomes of this work are a multi-channel correlator developed in a reconfigurable environment with new design methodology and I/O framework with software control application. The outcomes are used to demonstrate the potential of implementing DSP applications in hybrid CPU + FPGA architecture and to discuss existing challenges and suggest possible solutions.

<p>The P3RMA (Programmable, Parallel, and Predictable Random Memory Access) processor, currently being developed at Linköping University Sweden, is an attempt to solve the problems of parallel computing by utilizing a parallel memory subsystem and splitting the complexity of address computations with the complexity of data computations. It is targeted at embedded low power low cost computing for mobile phones, handsets and basestations among many others. By studying the radix-2 FFT using the P3RMA concept we have shown that even algorithms with a complex addressing pattern can be adapted to fully utilize a parallel datapath while only requiring additional simple addressing hardware. By supporting this algorithm with a SIMT instruction almost 100% utilization of the datapath can be achieved. A simulator framework for this processor has been proposed and implemented. This simulator has a very flexible structure featuring modular addition of new instructions and configurable hardware parameters. The simulator might be used by hardware developers and firmware developers in the future.</p>

<p>The goal of this bachelor thesis has been to investigate if the laboratory exercises in the courses digital filters and linear systems can be moved from matlab to a digital signal processor. The processor is a TMS320C6713 floating point processor mounted on a development board.</p><p> </p><p>The original laboratories have been implemented and analyzed and some suggested changes have been presented for the digital filter laboration. For the laboration in linear systems, the exercise can be implemented as it is today. Furthermore, a transmultiplexer has been implemented and tested for real time execution.</p><p> </p><p>Finally, an application programming interface has also been implemented, with common functions, used in the laboratories.</p><p> </p>

<p>The purpose of this thesis is to retarget a C compiler for a DSP processor. </p><p>Developing a new compiler from scratch is a major task. Instead, modifying an existing compiler so that it generates code for another target is a common way to develop compilers for new processors. </p><p>This is called retargeting. This thesis describes how this was done with the LCC C compiler for the Motorola DSP56002 processor.</p>

<p>Examensarbetets syfte var att skapa ett frekvensspektrum för ljud. För att representera detta frekvensspektrum används staplar av lysdioder. Systemet implementeras på ett Altera DE2 utvecklingskort. Olika sätt för att skapa dessa frekvensuppdelningar har testats och olika metoder för att lösa dessa har också testats.</p><p>Den slutliga implementeringen består av en filterbank som utnyttjar nersampling för att återanvända filter och sänka ordningen på dessa. Det största problemet var att få plats med allt på den FPGA som användes. Genom att byta till en lite mer komplicerad men effektivare filterstruktur så löstes detta problem och vi fick även gott om utrymme över.</p><p>Manualer och datablad har inte alltid varit lätta att tolka och ibland har andra metoder använts än de som beskrivs i dessa manualer med tips från support forum och handledare. Det finns vissa förbättringar att göra och vissa saker skulle kunnat göras annorlunda för att spara resurser med ett lite sämre resultat. När projektet var klart hade alla krav som ställts uppfyllts.</p>

<p>Under 20 års tid har Perimed AB utvecklat och tillverkat LDPM- och LDPI-instrument som är baserade på en analog filterkonstruktion. De analoga komponenterna i konstruktionen är komplexa och icke-linjära med hänsyn till frekvens och de driver även med temperaturen. Funktionen hos konstruktionen beror också kraftigt av att de analoga komponenterna trimmas in under produktionen.</p><p>Det här examensarbetet syftar till att ta fram en alternativ design baserad kring en digital signal processor. Den digitala signalbehandlingsmetod som beskrivs baseras på väl förankrade laser-Doppler perfusionsteorier. Den implementerade signalbehandlingsalgoritmen beräknar perfusionen ur en samplad fotodetektorström, som har filtrerats till AC- och DC-komponenter med hjälp av ett analogt detektorkort. Algoritmen producerar en råperfusionssignal genom att beräkna en frekvensviktad summa av fotodetektorströmmens effektspektrum. Kompensation för detektorns brus och normalisering med ljusintensitet har också implementerats.</p><p>Den presenterade implementationen har verifierats mot ett exemplar av LDPM-enheten PF 5010 som har använts som referensinstrument vid alla mätningar. Mätningar in vitro har påvisat liknande mätresultat som referensinstrumentet för en referensvätska med hög perfusion och även för ett statiskt mätobjekt. Vidare har implementationen verifierats med mätningar in vivo på hud, vilket har påvisat nära nog identiska signalnivåer och gensvar på värmeprovokationer som referensinstrumentet.</p><p>Den demonstrerade uppfinningen förenklar tillverkningen av instrumenten eftersom antalet komponenter reduceras avsevärt och därmed antalet produktionstester. Användandet av en DSP reducerar dessutom instrumentets temperaturkänslighet eftersom den ersätter flera temperaturkänsliga komponenter.</p> / <p>For 20 years Perimed AB have been developing and manufacturing LDPM and LDPI instruments based on an analog filter construction. The analog components in the construction are complex and suffer from non-linear frequency dependency and temperature drifts. The functionality of the design is also heavily depending on analog components which need to be trimmed in the production.</p><p>In this thesis, an alternative design employing a digital signal processor is presented. The signal processing method used is based on well established laser Doppler perfusion theories. The implemented signal processing algorithm calculates the perfusion from a sampled photodetector current, pre-filtered into AC and DC components by an analog detector card. The algorithm produces a raw perfusion signal by calculating a frequency weighted sum of the power spectral density, PSD, of the photocurrent. Detector noise compensation and light intensity normalization of the signal has also been implemented.</p><p>The presented digital implementation has been verified using the PF 5010 LDPM unit as a reference. In vitro measurements have shown similar behaviour as the reference in a highly perfused reference fluid as well as for a static scatterer. Furthermore, the DSP implementation has been verified on in vivo measurements of skin, showing nearly identical signal levels and response to heat provocation as the reference.</p><p>The demonstrated invention improves the manufacturability of the instruments since it reduces the number of electronic components significantly and thus, the amount of manufacturing tests. The DSP also reduces the temperature sensitivity of the instrument since it replaces several analog components sensitive to temperature changes.</p>

<p>This master thesis consists of implementation and evaluation of an AEC, Acoustic Echo Canceller, algorithm in a floating-point architecture. The most important question this thesis will try to answer is to determine benefits or drawbacks of using a floating-point architecture, relative a fixed-point architecture, to do AEC. In a telephony system there is two common forms of echo, line echo and acoustic echo. Acoustic echo is introduced by sound emanating from a loudspeaker, e.g. in a handsfree or speakerphone, being picked up by a microphone and then sent back to the source. The problem with this feedback is that the far-end speaker will hear one, or multiple, time-delayed version(s) of her own speech. This time-delayed version of speech is usually perceived as both confusing and annoying unless removed by the use of AEC. In this master thesis the performance of a floating-point version of a normalized least-mean-square AEC algorithm was evaluated in an environment designed and implemented to approximate live telephony calls. An instruction-set simulator and assembler available at the initiation of this master thesis were extended to enable; zero-overhead loops, modular addressing, post-increment of registers and register-write forwarding. With these improvements a bit-true assembly version was implemented capable of real-time AEC requiring 15 million instructions per second. A solution using as few as eight mantissa bits, in an external format used when storing data in memory, was found to have an insignificant effect on the selected AEC implementation’s performance. Due to the relatively low memory requirement of the selected AEC algorithm, the use of a small external format has a minor effect on the required memory size. In total this indicates that the possible reduction of the memory requirement and related energy consumption, does not justify the added complexity and energy consumption of using a floating-point architecture for the selected algorithm. Use of a floating-point format can still be advantageous in speech-related signal processing when the introduced time delay by a subband, or a similar frequency domain, solution is unacceptable. Speech algorithms that have high memory use and small introduced delay requirements are a good candidate for a floating-point digital signal processor architecture.</p>

<p>The scope for this thesis was to design a debug interface for a DSP (digital signal processor). The DSP is a research version of a Motorola 56000 that is designed for a project on asynchronous processor and for use in education.</p><p>The DSP and debug interface are controlled via a standard PC with RS232 interface equipped with Linux operation system.</p><p>In the project 4 blocks has been designed:</p><p>The first block can set the DSP core in debug mode or run mode. The second block sends a debug instruction to the DSP core, these debug instructions were prerequisite to the project. The third block enable read and write connection to the memory buses between the DSP core and the three memory blocks. The forth block can override the control signals to the memories from the DSP core.</p><p>The project also uses an UART for interpreting and sending control signals and data between the different blocks and the computer.</p><p>A text terminal program for Linux has also been programmed for handling the PC side communication.</p><p>The hardware has been constructed and tested together with a dummy DSP core and dummy memories, but it has not been tested together with the live DSP core.</p><p>The Linux program has been tested the same way and seems to do what it's supposed to, though it leaves a lot work to be easy to handle.</p>

<p>This thesis describes the design of a domain specific DSP processor. The thesis is divided into two parts. The first part gives some theoretical background, describes the different steps of the design process (both for DSP processors in general and for this project) and motivates the design decisions made for this processor. </p><p>The second part is a nearly complete design specification. </p><p>The intended use of the processor is as a platform for hardware acceleration units. Support for this has however not yet been implemented.</p>