<p>Denna rapport omfattar ett 15 poängs (22,5 högskolepoäng) examensarbete vid Karlstads universitet. Arbetet har utförts på plats hos BAE Systems Bofors i Karlskoga. Företaget ville kunna styra en radiostyrd leksaksstridsvagn med en laserpekare. En kamera ansluten till en digital signalprocessor (DSP) skulle kunna detektera var en laserpunkt befinner sig och styra stridsvagnen mot den.</p><p>Ett styrgränssnitt mellan DSP:n och leksaksstridsvagnen konstruerades och byggdes med hjälp av en programmerbar logisk krets. Leksaksstridsvagnens interna signalsystem analyserades. En manchesterkodad signal i form av ett 32-bitars seriellt kodord hittades, vilket ursprungligen kom från radiostyrningen. Ett styrgränssnitt konstruerades kring en CPLD (Complex Programmable Logic Device) vilken programmerades med VHDL (Very high speed integrated Hardware Description Language) som återskapar den Manchesterkodade styrsignalen.</p><p>Gränssnittet ansluter till DSP:n som kontrollerar stridsvagnens styrning och övriga funktioner till fullo. Kommunikationen mellan styrgränssnittet och DSP:n sker via ett parallellgränssnitt som är 16-bitar brett. 13 bitar är datasignaler och övriga tre är ”styrbitar” som konfigurerar gränssnittet. En applikation integrerades i projektet för att demonstrera styrgränssnittets funktion. DSP:n tolkar var en laserpunkt befinner sig inom ett kameraområde och skickar motsvarande styrsignaler till leksaksstridsvagnen.</p> / <p>This report consists of a 15 points (22.5 ECTS) Exam Degree project at Karlstad University. The work was done on location at BAE Systems Bofors AB in Karlskoga. The company wanted to control a radio controlled toy tank from a digital signal processor (DSP). A camera connected to the DSP locates the laser point and steers the toy tank towards it.</p><p>An interface using a programmable logic device was constructed that connects the DSP to the toy tank. The internal signals in the toy tank was analyzed and a Manchester coded signal in form of a 32-bit serial code word was detected. The code word originated from the radio controller. The control interface was built around a CPLD (Complex Programmable Logic Device) which was programmed in VHDL (Very high speed integrated Hardware Description Language). The control interface recreates the signal controlling the toy tank.</p><p>The interface connects the toy tank to the DSP which controls the toy tank and it’s functions to the full extent. Communication between the interface and the DSP is done via a 16 bit parallel connection. 13 of the bits are data bits and the remaining 3 are control bits that are used to set up the interface. An application was integrated in the project where the DSP is detecting a laser point. Corresponding signals to the laser points position where sent to the control interface to demonstrate the function of the interface.</p>

Detta är en rapport över mitt examensarbete som utfördes för Motion Control AB i Västerås. Uppgiften bestod i att ta fram en prototyp för en handhållen ljudlokalisator för döva. Projektet har inneburit arbete med allt från marknadsundersökningar till lödning. Projektet innehåller såväl analog elektronik som programmering. Mycket tid gick åt till själva förarbetet, kanske lite väl mycket då det kändes som halva tiden gick åt innan jag kunde komma igång och arbeta. Jag lyckades få fram en prototyp där allt fungerade förutom mikrofonerna, de visade sig vara för känsliga för att löda för hand. Dock så har projektet varit mycket lärorikt och intressant. / This is a report of my thesis work carried out for Motion Control AB in Västerås. The task was to develop a prototype for a handheld sound localizator for the deaf. The project has involved working with everything from market research to soldering. The project includes both analog electronics as well as programming. Much time was spent on the preparatory work, maybe a little too much when it seemed like half the time was spent before I could get started and work. I managed to get a functional prototype except for the microphones, as they proved to be too sensitive to solder by hand. However, the project has been very educational and interesting.

<p>This Master thesis describes the benchmarking of a DSP processor. Benchmarking means measuring the performance in some way. In this report, we have focused on the number of instruction cycles needed to execute certain algorithms. The algorithms we have used in the benchmark are all very common in signal processing today. </p><p>The results we have reached in this thesis have been compared to benchmarks for other processors, performed by Berkeley Design Technology, Inc. </p><p>The algorithms were programmed in assembly code and then executed on the instruction set simulator. After that, we proposed changes to the instruction set, with the aim to reduce the execution time for the algorithms. </p><p>The results from the benchmark show that our processor is at the same level as the ones tested by BDTI. Probably would a more experienced programmer be able to reduce the cycle count even more, especially for some of the more complex benchmarks.</p>

The increasing number of portable devices, such as Smart phones, laptops, tablets etc, has certainly pushed up the market of wireless communication systems. These high performance devices need to comply with the strict requirements in terms of energy consumption. Battery capacity progress is relatively slower compared with the technological evolution of devices. Therefore, energy consumption issues can be solved when innovations are introduced in the processor design and architecture side. This thesis focuses on the word-length optimization for algorithms that run on wireless receivers with multiple antennas (MIMO). The study was made for the signal’s quantization. Earlier experiments have shown that the signal conversion from floating–point to fixed–point representation requires unaffordable Bit-Error-Rate (BER) simulations that may last for hours or even for days. During this thesis, a new divide-and-conquer method has been developed. It faces the ‘quantization problem’ hierarchically by grouping signals and exploiting the correlation between quantization error and Gaussian additive noise. BER simulations were limited by involving noise simulations. This method was successfully applied to a highly adaptive digital signal processing (DSP) algorithm, improving the total simulation time up to 84%. / Η αυξανόμενος αριθμός των κινητών συσκευών, όπως τα Smart phones, laptops, tablets κλπ, έχει εκτοξεύσει υψηλά την αγορά των ασύρματων συσκευών επικοινωνίας. Αυτές οι συσκευές υψηλής τεχνολογίας πρέπει να συμμορφώνονται με τις αυστηρές απαιτήσεις στα πλαίσια της κατανάλωσης ενέργειας. Η πρόοδος της αύξησης της χωρητικότητας της μπαταρίας χαρακτηρίζεται σχετικά αργή συγκρινόμενη με την τεχνολογική εξέλιξη των συσκευών. Ως εκ τούτου, θέματα που αφορούν στην κατανάλωση ενέργειας αντιμετωπίζονται όταν πραγματοποιούνται καινοτομίες στον τομέα της σχεδίασης και αρχιτεκτονικής επεξεργαστών. Η παρούσα διατριβή εστιάζει στην βελτιστοποίηση των μηκών λέξεων (word-length optimization) για αλγορίθμους που τρέχουν σε ασύρματους δέκτες με πολλαπλές κεραίες (MIMO). Η μελέτη αφορά στην κβαντοποίηση σημάτων (signal quantization). Προηγούμενα πειράματα έδειξαν ότι η μετατροπή των σημάτων άπειρης ακρίβειας (floating-point) σε πεπερασμένης (fixed-point) απαιτεί χρονοβόρες Bit-Error-Rate (BER) προσομοιώσεις που μπορεί να διαρκέσουν πολλές ώρες ή ακόμη και ημέρες. Κατά την διάρκεια της διπλωματικής εργασίας, αναπτύχθηκε μία νέα divide-and-conquer μέθοδος. Αντιμετωπίζει το πρόβλημα της κβαντοποίησης ιεραρχικά ομαδοποιώντας τα σήματα και εκμεταλλεύοντας την συσχέτιση του σφάλματος κβαντοποίσης (quantization error) και του προσθετικού Γκαουσιανού θορύβου (AWGN). Οι BER προσoμοιώσεις περιορίστηκαν περιλαμβάνοντας προσομοιώσεις θορύβου (noise simulations). Αυτή η μέθοδος εφαρμόστηκε επιτυχώς σε πολύπλοκο αλγόριθμο υψηλής προσαρμοστικότητας για DSP, βελτιώνοντας τον συνολικό χρόνο προσομοίωσης έως και 84%.

This Master thesis describes the benchmarking of a DSP processor. Benchmarking means measuring the performance in some way. In this report, we have focused on the number of instruction cycles needed to execute certain algorithms. The algorithms we have used in the benchmark are all very common in signal processing today. The results we have reached in this thesis have been compared to benchmarks for other processors, performed by Berkeley Design Technology, Inc. The algorithms were programmed in assembly code and then executed on the instruction set simulator. After that, we proposed changes to the instruction set, with the aim to reduce the execution time for the algorithms. The results from the benchmark show that our processor is at the same level as the ones tested by BDTI. Probably would a more experienced programmer be able to reduce the cycle count even more, especially for some of the more complex benchmarks.

We introduce an extensible knowledge based tool for idiom (pattern) recognition in DSP(digital signal processing) programs. Our tool utilizesfunctionality provided by the Cetus compiler infrastructure fordetecting certain computation patterns that frequently occurin DSP code. We focus on recognizing patterns for for-loops andstatements in their bodies as these often are the performance criticalconstructs in DSP applications for which replacementby highly optimized, target-specific parallel algorithms will bemost profitable. For better structuring and efficiency of patternrecognition, we classify patterns by different levels of complexitysuch that patterns in higher levels are defined in terms of lowerlevel patterns.The tool works statically on the intermediate representation(IR). It traverses the abstract syntax tree IR in post-orderand applies bottom-up pattern matching, at each IR nodeutilizing information about the patterns already matched for itschildren or siblings.For better extensibility and abstraction,most of the structuralpart of recognition rules is specified in XML form to separatethe tool implementation from the pattern specifications.Information about detected patterns will later be used foroptimized code generation by local algorithm replacement e.g. for thelow-power high-throughput multicore DSP architecture ePUMA.

Les travaux de thèse s'intéressent à la problématique de contrôle et de communication dans le domaine de la conception des systèmes numériques embarqués pour les applications de télécommunication de quatrième génération. La complexité des applications couplée aux besoins de productivité croissants impose de repenser les méthodologies de conception et les architectures sous jacentes. Afin de lever ces verrous, nous proposons plusieurs contributions originales. En effet, une méthodologie d'exploration d'un espace de conception ainsi qu'une architecture basée sur des noeuds de traitements homogènes et flexibles interconnectés à travers un réseau sur silicium sont proposées. Chaque noeud de traitement possède plusieurs blocs visant à exécuter efficacement et dynamiquement les applications de télécommunication. Pour répondre aux contraintes de faible consommation, nous proposons plusieurs solutions innovantes afin de minimiser cette métrique notamment au travers de techniques de migration de tâches. / This PhD research aims to solve challenges about control and communication in the design of digital embedded systems for 4G telecom applications. The application complexity added to the increasing productivity gap force to think about new design methodologies and the underlying architectures. Several new research directions is proposed in this work. A methodology for design space exploration and a digital architecture based on homogeneous and flexible processing units interconnected by a Network-on-Chip is proposed. A processing unit is a cluster of DSPs controled by a MIPS processor to compute telecom applications. To meet low power constraints, we propose optimization techniques based on resource management including task migration.

As the internet user base increases over the years, so do the logistic difficulties of handling higher and higher volumes of data. This large amount of information is now being exploited by Artificial Intelligence algorithms to deliver value to our society on a global scale. Among all the algorithms employed, the widespread adoption of Neural Networks in industrial settings is promoting the automation of tasks previously unsolvable by computers. As of today, efficiency limits the applicability of such technology on Big Data and efforts are being put to develop new acceleration solutions.In this project, we analyzes the computational capabilities of a multicore Digital Signal Processor called the EMCA (Ericsson Many-Core Architecture) when it comes to executing Neural Networks. The EMCA is a proprietary chip used for real-time processing of data in the pipeline of a Radio Base Station.We developed an inference engine to run Neural Networks on the EMCA. The software of such engine has been produced using a proprietary operating system called Flake OS, which runs on the EMCA. On top of the inference engine, we wrote a neural network squeezing pipeline based on quantization. On MNIST, the quantization algorithm can reduce the size of the networks by 4x folds with sub 1% accuracy degradation. The inference engine has been optimized to exploit the quantization utility and can run quantized neural networks. Tests have been done to understand the direct implications of using such algorithm. We show that the quantization is indeed beneficial for inference on DSPs.Finally, the EMCA has demonstrated state of the art computational capabilities for neural network inferencing. / Liksom antalet internetanvändare årligen ökar, så gör också de logistiska svårigheterna att hantera större och större volymer av data. Denna stora mängd av information används nu av artificiell intelligens algoritmer för att leverera värde till vårt samhälle på en global skala. Av alla använda algoritmer, så möjliggör det utbredda införandet av neurala nätverk i industriella omgivningar, att uppgifter som tidigare inte kunde lösas av datorer nu kan automatiseras. Idag så finns det effektivitetsfaktorer som begränsar användbarheten av dessa tekniker för stora datamängder och insatser görs därför för att utveckla nya accelererade lösningar. I det här projektet så analyserar vi beräkningsförmågan av en multicore digital signalprocessor kallad EMCA (Ericsson Many-Core Architecture) för att exekvera neurala nätverk. EMCAn är ett proprietärt mikro-chip som används för real-tids beräkningar av data i pipelinen av en radiobasstation. Vi utvecklade en inferensmotor för att köra neurala nätverk på EM-CAn. Mjukvaran för motorn använde ett proprietärt operativsystem, kallat Flake OS, som körs på EMCAn. Ovanpå inferensmotorn skrev vi en pipeline för att reducera storleken av det neurala nätverket med hjälp av kvantisering. På MNIST så kan kvantiseringsalgorit-men minska storleken av näten upp till 4 gånger med under 1% precisionsdegradering. Inferensmotorn har optimerats för att utnyttja kvantiseringsfunktionen och kan exekvera kvantiserade neurala nätverk. Tester har gjorts för att förstå de direkta följderna av att använda sådana algoritmer. Vi visar att kvantisering verkligen är till nytta för att göra inferens på DSPer. Slutligen, EMCAn har demonstrerat toppmodern beräkningsförmåga för inferens av neurala nätverk.

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / Signal conditioning is a critical element in all data telemetry systems. Data from all sensors must be band limited prior to digitization and transmission to prevent the potentially disastrous effects of aliasing. While the 6th order analog low-pass Butterworth filter has long been the de facto standard for data channel filtering, advances in digital signal processing techniques now provide a potentially better alternative. This paper describes the challenges in developing a flexible approach to adaptable data channel filtering using DSP techniques. Factors such as anti-alias filter requirements, time correlated sampling, decimation and filter delays will be discussed. Also discussed will be the implementation and relative merits and drawbacks of various symmetrical FIR and IIR filters. The discussion will be presented from an intuitive and practical perspective as much as possible.

Students at Uppsala University have for some years been given the opportunity to take courses in subjects directly, or indirectly, related to the fields of signal processing and signal analysis. According to the directors of these courses, a considerable number of students are recurringly having difficulties grasping different concepts related to this field of study. This report covers a tool that easily allows teachers to visualize and listen to different manipulations of signals, which should help students get an intuitive understanding of the subject. Features of the system include multiple kinds of analog filters, sampling with variable settings and zero-order hold reconstruction. The finished system is flexible, tunable and modifiable to the teachers every need, making it usable for a wide variety of courses involving signal processing. The system meets its requirements even though individual components’ results de- viate slightly from ideal values. / Studenter vid Uppsala Universitet har, under ett antal år, givits möjligheten att läsa kurser inom ämnen direkt, eller indirekt, relaterade till signalbehandling/signalanalys. Enligt kursansvariga för dessa kurser har en ansenlig andel av studenterna svårigheter med att förstå en del av de begrepp och fenomen som förekommer under kurserna. Denna rapport behandlar ett verktyg som ger lärare i dessa kurser möjlighet att på ett enkelt sätt visualisera och lyssna på olika manipulationer av signaler, vilket bör hjälpa studenterna bygga en intuition för ämnet. Systemets olika funktioner inkluderar flera olika typer av analoga filter, sampling med olika inställningar, och så kallad ’Zero-Order-Hold’ rekonstruktion. Det resulterande systemet är flexibelt, inställbart och modifierbart till användarens behov, vilket gör det applicerbart i flera kurser som innefattar signalbehandling/analys. Systemet möter kraven som ställs, även fast resultaten hos individuella komponenter avviker aningen från ideala värden.