This thesis presents a novel self-powered infrastructural traffic monitoring approach that estimates traffic information by combining three detection techniques. The traffic information can be obtained from the presented approach includes vehicle counts, speed estimation and vehicle classification based on size. Two categories of sensors are used including IR Lidar and IR camera. With the two sensors, three detection techniques are used: Time of Flight (ToF) based, vision based and Laser spot flow based. Each technique outputs observations about vehicle location at different time step. By fusing the three observations in the framework of Kalman filter, vehicle location is estimated, based on which other concerned traffic information including vehicle counts, speed and class is obtained. In this process, high reliability is achieved by combing the strength of each techniques. To achieve self-powering, a dynamic power management strategy is developed to reduce system total energy cost and optimize power supply in traffic monitoring based on traffic pattern recognition. The power manager attempts to adjust the power supply by reconfiguring system setup according to its estimation about current traffic condition. A system prototype has been built and multiple field experiments and simulations were conducted to demonstrate traffic monitoring accuracy and power reduction efficacy. / Master of Science

With FinFET based Application Specific Integrated Circuit (ASIC) designs delivering on the promises of scalability, performance, and power, the road ahead is bumpy with technical challenges in building efficient ASICs. Designers can no longer rely on the ‘auto-scaling’ power reduction that follows technology node scaling, in these times when 7nm presents itself as a ‘long-lived’ node. This leads to the need for early power analysis and reduction flows that are incorporated into the ASIC Intellectual Property (IP) design flow. This leads to a focus on power-efficient design in addition to being functionally efficient. Power inefficiency related hotspots are the leading causes of chip re-spins, and a guideline methodology to design blocks in a power-efficient manner leads to a power-efficient design of the Integrated Circuits (ICs). This alleviates the intensity of cooling requirements and the cost. The Common Memory controller is one of the leading consumers of power in the ASIC designs at Ericsson. This Thesis focusses on developing a power analysis and reduction flow for the common memory controller by connecting the verification environment of the block to low-level power analysis tools, using motivated test cases to collect power metrics, thereby leading to two main goals of the Thesis, characterization and optimization of the block for power. This work also includes an energy efficiency perspective through the Differential Energy Analysis technique, initiated by Qualcomm and Ansys, to improve the flow by improving the test cases that help uncover power inefficiencies/bugs and therefore optimize the block. The flow developed in the Thesis fulfills the goals of characterizing and optimizing the block. The characterization data is presented to provide an idea of the type of data that can be collected and useful for SoC architects and designers in planning for future designs. The characterization/profiling data collected from the blocks collectively contribute to the Electronic System-level power analysis that helps correlate the ASIC power estimate to silicon. The work also validates the flow by working on a specific sub-block, identifying possible power bugs, modifying the design and validating improved performance and thereby, validating the flow. / Med FinFET-baserade applikationsspecifika integrerade kretsar (ASIC) -konstruktioner som ger löften om skalbarhet, prestanda och kraft är vägen framåt ojämn med tekniska utmaningar när det gäller att bygga effektiva ASIC: er. Formgivare kan inte längre lita på den "autoskalande" effektminskningen som följer teknisk nodskalning, i dessa tider då 7nm presenterar sig som en "långlivad" nod. Detta leder till behovet av tidig kraftanalys och reduktionsflöden som är integrerade i ASIC Intellectual Property (IP) designflöde. Detta leder till fokus på energieffektiv design förutom att det är funktionellt effektivt. Krafteffektivitetsrelaterade hotspots är de ledande orsakerna till respins av chip, och en riktlinjemetodik för att konstruera block på ett energieffektivt sätt leder till energieffektiv design av Integrated Circuits (ICs). Detta lindrar intensiteten hos kylbehovet och kostnaden. Common Memory-kontrollen är en av de ledande energikonsumenterna i ASIC-designen hos Ericsson. Denna avhandling fokuserar på att utveckla en effektanalys och reduktionsflöde för den gemensamma minneskontrollern genom att ansluta verifieringsmiljön för blocket till lågnivåeffektanalysverktyg, med hjälp av motiverade test caser för att samla effektmätvärden, vilket leder till två huvudmål för avhandlingen, karakterisering och optimering av blocket för kraft. Detta arbete inkluderar också energieffektivitetsperspektiv genom Differential Energy Analys-teknik, initierad av Qualcomm och Ansys, för att förbättra flödet genom att förbättra test cases som hjälper till att upptäcka effekteffektivitet / buggar och därför optimera blocket. Flödet som utvecklats i avhandlingen uppfyller målen att karakterisera och optimera blocket. Karaktäriseringsdata presenteras för att ge en uppfattning om vilken typ av data som kan samlas in och vara användbara för SoC-arkitekter och designers i planering för framtida mönster. Karaktäriserings/ profileringsdata som samlats in från blocken bidrar tillsammans till effektanalysen för elektronisk systemnivå som hjälper till att korrelera ASIC-effektberäkningen till kisel. Arbetet validerar också flödet genom att arbeta på ett specifikt underblock, identifiera möjliga effektbuggar, modifiera utforma och validera förbättrad prestanda och därmed validera flödet.

Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação. / Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.

Le travail présenté vise à mettre en place une méthodologie pour le suivi en service de la fatigue mécanique pour l’ombilical dynamique d’un système EMR flottant. L’approche envisagée consiste à simuler à l’aide d’outils numériques la réponse de l’ombilical aux cas de chargement observés sur site. Le post-traitement des résultats de ces simulations devant permettre d’accéder à différentes quantités d’intérêt en tout point du câble. Pour quantifier et réduire l’incertitude sur la réponse calculée de l’ombilical ce dernier doit être instrumenté. Un certain nombre de paramètres du modèle numérique feront alors l’objet d’une calibration régulière pour suivre l’évolution des caractéristiques de l’ombilical susceptibles d’évoluer. Dans ce contexte ce manuscrit présente et compare différentes méthodes pour analyser la sensibilité de la réponse de l’ombilical aux paramètres susceptibles d’être suivis. L’objectif est notamment d’orienter le choix des mesures à mettre en oeuvre. L’analyse en composantes principales permet pour cela d’identifier les principaux modes de variation de la réponse de l’ombilical en réponse aux variations des paramètres étudiés. Différentes approches sont également envisagées pour la calibration des paramètres suivis,avec en particulier le souci de quantifier l’incertitude restante sur le dommage. Les méthodes envisagées sont coûteuses en nombre d’évaluations du modèle numérique et ce dernier est relativement long à évaluer. L’emploi de méta-modèles en substitution des simulations numériques apparait donc nécessaire, et là encore différentes options sont considérées. La méthodologie proposée est appliquée à une configuration simplifiée d’ombilical dans des conditions inspirées du projet FLOATGEN. / The present work introduces a methodology to monitor fatigue damage of the dynamic power cable of a floating wind turbine. The suggested approach consists in using numerical simulations to compute the power cable response at the sea states observed on site. The quantities of interest are then obtained in any location along the cable length through the post-treatment of the simulations results. The cable has to be instrumented to quantify and to reduce the uncertainties on the calculated response of the power cable. Indeed some parameters of the numerical model should be calibrated on a regular basis in order to monitor the evolution of the cable properties that might change over time. In this context, this manuscript describes and compares various approaches to analyze the sensitivity of the power cable response to the variations of the parameters to be monitored. The purpose is to provide guidance in the choice of the instrumentation for the cable. Principal components analysis allows identifying the main modes of power cable response variations when the studied parameters are varied. Various methods are also assessed for the calibration of the monitored cable parameters. Special care is given to the quantification of the remaining uncertainty on the fatigue damage. The considered approaches are expensive to apply as they require a large number of model evaluations and as the numerical simulations durations are quite long. Surrogate models are thus employed to replace the numerical model and again different options are considered. The proposed methodology is applied to a simplified configuration which is inspired by the FLOATGEN project.

No description available.

We present a generic proof methodology to automatically prove correctness of design transformations introduced at the Register-Transfer Level (RTL) to achieve lower power dissipation in hardware systems. We also introduce a new algorithm to reduce switching activity power dissipation in microprocessors. We further apply our technique in a completely different domain of dynamic power management of Systems-on-Chip (SoCs). We demonstrate our methodology on real-life circuits. In this thesis, we address the dual problem of transforming hardware systems at higher levels of abstraction to achieve lower power dissipation, and a reliable way to verify the correctness of the afore-mentioned transformations. The thesis is in three parts. The first part introduces Instruction-driven Slicing, a new algorithm to automatically introduce RTL/System level annotations in microprocessors to achieve lower switching power dissipation. The second part introduces Dedicated Rewriting, a rewriting based generic proof methodology to automatically prove correctness of such high-level transformations for lowering power dissipation. The third part implements dedicated rewriting in the context of dynamically managing power dissipation of mobile and hand-held devices. We first present instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level in order to achieve lower power dissipation. Our technique automatically annotates existing RTL code to optimize the circuit for lowering power dissipated by switching activity. Our technique can be applied at the architectural level as well, achieving similar power gains. We first demonstrate our technique on architectural and RTL models of a 32-bit OpenRISC pipelined processor (OR1200), showing power gains for the SPEC2000 benchmarks. These annotations achieve reduction in power dissipation by changing the logic of the design. We further extend our technique to an out-of-order superscalar core and demonstrate power gains for the same SPEC2000 benchmarks on architectural and RTL models of PUMA, a fixed point out-of-order PowerPC microprocessor. We next present dedicated rewriting, a novel technique to automatically prove the correctness of low power transformations in hardware systems described at the Register Transfer Level. We guarantee the correctness of any low power transformation by providing a functional equivalence proof of the hardware design before and after the transformation. Dedicated rewriting is a highly automated deductive verification technique specially honed for proving correctness of low power transformations. We provide a notion of equivalence and establish the equivalence proof within our dedicated rewriting system. We demonstrate our technique on a non-trivial case study. We show equivalence of a Verilog RTL implementation of a Viterbi decoder, a component of the DRM System-On-Chip (SoC), before and after the application of multiple low power transformations. We next apply dedicated rewriting to a broader context of holistic power management of SoCs. This in turn creates a self-checking system and will automatically flag conflicting constraints or rules. Our system will manage power constraint rules using dedicated rewriting specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlessly cooperate between hardware and software constraints to achieve maximum platform power optimization dynamically during execution. We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform. Finally, we give a proof of instruction-driven slicing. We first prove that the annotations automatically introduced in the OR1200 processor preserve the original functionality of the machine using the ACL2 theorem prover. Then we establish the same proof within our dedicated rewriting system, and discuss the merits of such a technique and a framework. In the context of today's shrinking hardware and mobile internet devices, lowering power dissipation is a key problem. Verifying the correctness of transformations which achieve that is usually a time-consuming affair. Automatic and reliable methods of verification that are easy to use are extremely important. In this thesis we have presented one such transformation, and a generic framework to prove correctness of that and similar transformations. Our methodology is constructed in a manner that easily and seamlessly fits into the design cycle of creating complicated hardware systems. Our technique is also general enough to be applied in a completely different context of dynamic power management of mobile and hand-held devices. / text

abstract: Semiconductor scaling technology has led to a sharp growth in transistor counts. This has resulted in an exponential increase on both power dissipation and heat flux (or power density) in modern microprocessors. These microprocessors are integrated as the major components in many modern embedded devices, which offer richer features and attain higher performance than ever before. Therefore, power and thermal management have become the significant design considerations for modern embedded devices. Dynamic voltage/frequency scaling (DVFS) and dynamic power management (DPM) are two well-known hardware capabilities offered by modern embedded processors. However, the power or thermal aware performance optimization is not fully explored for the mainstream embedded processors with discrete DVFS and DPM capabilities. Many key problems have not been answered yet. What is the maximum performance that an embedded processor can achieve under power or thermal constraint for a periodic application? Does there exist an efficient algorithm for the power or thermal management problems with guaranteed quality bound? These questions are hard to be answered because the discrete settings of DVFS and DPM enhance the complexity of many power and thermal management problems, which are generally NP-hard. The dissertation presents a comprehensive study on these NP-hard power and thermal management problems for embedded processors with discrete DVFS and DPM capabilities. In the domain of power management, the dissertation addresses the power minimization problem for real-time schedules, the energy-constrained make-span minimization problem on homogeneous and heterogeneous chip multiprocessors (CMP) architectures, and the battery aware energy management problem with nonlinear battery discharging model. In the domain of thermal management, the work addresses several thermal-constrained performance maximization problems for periodic embedded applications. All the addressed problems are proved to be NP-hard or strongly NP-hard in the study. Then the work focuses on the design of the off-line optimal or polynomial time approximation algorithms as solutions in the problem design space. Several addressed NP-hard problems are tackled by dynamic programming with optimal solutions and pseudo-polynomial run time complexity. Because the optimal algorithms are not efficient in worst case, the fully polynomial time approximation algorithms are provided as more efficient solutions. Some efficient heuristic algorithms are also presented as solutions to several addressed problems. The comprehensive study answers the key questions in order to fully explore the power and thermal management potentials on embedded processors with discrete DVFS and DPM capabilities. The provided solutions enable the theoretical analysis of the maximum performance for periodic embedded applications under power or thermal constraints. / Dissertation/Thesis / Ph.D. Computer Science 2012

Energy consumption has become a first-class optimization goal in design and implementation of data-intensive computing systems. This is particularly true in the design of database management systems (DBMS), which is one of the most important servers in software stack of modern data centers. Data storage system is one of the essential components of database and has been under many research efforts aiming at reducing its energy consumption. In previous work, dynamic power management (DPM) techniques that make real-time decisions to transition the disks to low-power modes are normally used to save energy in storage systems. In this research, we tackle the limitations of DPM proposals in previous contributions and design a dynamic energy-aware disk storage system in database servers. We introduce a DPM optimization model integrated with model predictive control (MPC) strategy to minimize power consumption of the disk-based storage system while satisfying given performance requirements. It dynamically determines the state of disks and plans for inter-disk data fragment migration to achieve desirable balance between power consumption and query response time. Furthermore, via analyzing our optimization model to identify structural properties of optimal solutions, a fast-solution heuristic DPM algorithm is proposed that can be integrated in large-scale disk storage systems, where finding the most optimal solution might be long, to achieve near-optimal power saving solution within short periods of computational time. The proposed ideas are evaluated through running simulations using extensive set of synthetic workloads. The results show that our solution achieves up to 1.65 times more energy saving while providing up to 1.67 times shorter response time compared to the best existing algorithm in literature. Stream join is a dynamic and expensive database operation that performs join operation in real-time fashion on continuous data streams. Stream joins, also known as window joins, impose high computational time and potentially higher energy consumption compared to other database operations, and thus we also tackle energy-efficiency of stream join processing in this research. Given that there is a strong linear correlation between energy-efficiency and performance of in-memory parallel join algorithms in database servers, we study parallelization of stream join algorithms on multicore processors to achieve energy efficiency and high performance. Equi-join is the most frequent type of join in query workloads and symmetric hash join (SHJ) algorithm is the most effective algorithm to evaluate equi-joins in data streams. To best of our knowledge, we are the first to propose a shared-memory parallel symmetric hash join algorithm on multi-core CPUs. Furthermore, we introduce a novel parallel hash-based stream join algorithm called chunk-based pairing hash join that aims at elevating data throughput and scalability. We also tackle parallel processing of multi-way stream joins where there are more than two input data streams involved in the join operation. To best of our knowledge, we are also the first to propose an in-memory parallel multi-way hash-based stream join on multicore processors. Experimental evaluation on our proposed parallel algorithms demonstrates high throughput, significant scalability, and low latency while reducing the energy consumption. Our parallel symmetric hash join and chunk-based pairing hash join achieve up to 11 times and 12.5 times more throughput, respectively, compared to that of state-of-the-art parallel stream join algorithm. Also, these two algorithms provide up to around 22 times and 24.5 times more throughput, respectively, compared to that of non-parallel (sequential) stream join computation where there is one processing thread.

Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação. / Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.

Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação. / Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.