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Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%. / Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.

Les applications temps réel modernes deviennent plus exigeantes en termes de ressources et de débit amenant la conception d'architectures multiprocesseurs. Ces systèmes, des équipements embarqués au calculateur haute performance, sont, pour des raisons d'autonomie et de fiabilité, confrontés des problèmes cruciaux de consommation d'énergie. Pour ces raisons, cette thèse propose de nouvelles techniques d'optimisation de la consommation d'énergie dans l'ordonnancement de systèmes multiprocesseur. La premiére contribution est un algorithme d'ordonnancement hiérarchique á deux niveaux qui autorise la migration restreinte des tâches. Cet algorithme vise á réduire la sous-optimalité de l'algorithme global EDF. La deuxiéme contribution de cette thèse est une technique de gestion dynamique de la consommation nommée Assertive Dynamic Power Management (AsDPM). Cette technique, qui régit le contrôle d'admission des tâches, vise á exploiter de manière optimale les modes repos des processeurs dans le but de réduire le nombre de processeurs actifs. La troisiéme contribution propose une nouvelle technique, nommée Deterministic Stretch-to-Fit (DSF), permettant d'exploiter le DVFS des processeurs. Les gains énergétiques observés s'approchent des solutions déjà existantes tout en offrant une complexité plus réduite. Ces techniques ont une efficacité variable selon les applications, amenant á définir une approche plus générique de gestion de la consommation appelée Hybrid Power Management (HyPowMan). Cette approche sélectionne, en cours d'exécution, la technique qui répond le mieux aux exigences énergie/performance.

Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%. / Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.

Algumas técnicas foram criadas com o objetivo de reduzir o consumo de potência, dentre elas o uso de Mútiplas Tensões de Alimentação ajustadas de Forma Dinâmica(Multiple Dynamic Supply Voltage - MDSV). Essa técnica visa reduzir o consumo dinâmico utilizando pelo menos três tensões de alimentação diferentes dentro do chip. Para isso, é necessário que circuitos especiais de proteção sejam adicionados ao chip. Os conversores de tensão tem como objetivo aumentar ou diminuir o nível de tensão do sinal de entrada. O custo de introduzir os conversores de tensão, em circuitos que utilizam a técnica MDSV, é alto. Uma vez que isso causa aumento da área total e altera a temporização do chip. Com base nisso, esse trabalho propõem adicionar um caminho alternativo para a corrente, desviando e desligando os conversores de tensão enquanto eles não são necessários. Cabe salientar que alguns conversores de tensão ficam sem utilidade por causa da característica dinâmica dos circuitos contruídos usando MDSV. Com isso, neste trabalho é proposta uma nova construção para os conversores de tensão utilizados em conjunto com o MDSV. Nas simulações elétricas, os circuitos contendo essa nova construção apresentaram redução no tempo de propagação de até 13%, em comparação aos circuitos tradicionalmente utilizados para conversão de tensão. Além da redução no tempo de atraso, foram alcançadas reduções no consumo de potência na ordem de 14%. / Some techniques have been created with the purpose of reducing power consumption, among them the Multiple Dynamic Supply Voltage (MDSV). This technique aims to reduce the dynamic consumption using at least three different supply voltages inside the chip. Therefore, it is necessary that special protection circuits to be added to the chip. Level shifter aims to increase or decrease the voltage level of the input signal. The cost of introducing the voltage converters in circuits using the MDSV technique is high. As this causes increased total area and changes the timing of the chip. Based on this, this paper proposes to add an alternate path for current, deflecting off and the voltage converters as they are not required. It should be noted that some voltage converters are useless because of the dynamic characteristic of contruidos circuits using MDSV. Thus, this work proposes a new construction for the voltage converters used in conjunction with MDSV. In electric simulations, the circuit containing this new construction decreased to 13% in the propagation time in comparison to the circuits traditionally used for voltage conversion. In addition to reducing the delay time, reductions were achieved in the power consumption on the order of 14%.

Rising concerns related to the effects of traffic congestion have led to the search for alternative transportation solutions. Advances in battery technology have resulted in an increase of electric vehicles (EVs), which serve to reduce the impact of many of the negative consequences of congestion, including pollution and the cost of wasted fuel. Furthermore, the energy-efficiency and quiet operation of electric motors have made feasible concepts such as Urban Air Mobility (UAM), in which electric aircraft transport passengers in dense urban areas prone to severe traffic slowdowns. Electrified transportation may be the solution needed to combat urban gridlock, but many logistical questions related to the design and operation of the resultant transportation networks remain to be answered. This research begins by examining the near-term effects of EV charging networks. Stationary plug-in methods have been the traditional approach to recharge electric ground vehicles; however, dynamic charging technologies that can charge vehicles while they are in motion have recently been introduced that have the potential to eliminate the inconvenience of long charging wait times and the high cost of large batteries. Using an agent-based model verified with traffic data, different network designs incorporating these dynamic chargers are evaluated based on the predicted benefit to EV drivers. A genetic optimization is designed to optimally locate the chargers. Heavily-used highways are found to be much more effective than arterial roads as locations for these chargers, even when installation cost is taken into consideration. This work also explores the potential long-term effects of electrified transportation on urban congestion by examining the implementation of a UAM system. Interdependencies between potential electric air vehicle ranges and speeds are explored in conjunction with desired network structure and size in three different regions of the United States. A method is developed to take all these considerations into account, thus allowing for the creation of a network optimized for UAM operations when vehicle or topological constraints are present. Because the optimization problem is NP-hard, five heuristic algorithms are developed to find potential solutions with acceptable computation times, and are found to be within 10% of the optimal value for the test cases explored. The results from this exploration are used in a second agent-based transportation model that analyzes operational parameters associated with UAM networks, such as service strategy and dispatch frequency, in addition to the considerations associated with network design. General trends between the effectiveness of UAM networks and the various factors explored are identified and presented.

Emerging mobile platforms integrate heterogeneous, multicore processors to efficiently deal with the heterogeneity of data (in magnitude, type, and quality). The main goal is to achieve a high degree of energy-proportionality which corresponds with the nature and fluctuation of mobile workloads. Most existing power and energy consumption analyses of these architectures rely on simulation or static benchmarks neither of which truly reflects the type of workload the processors handle in reality. By contrast, we generate two types of stochastic workloads and employ four types of dynamic voltage and frequency scaling (DVFS) policies to investigate the energy proportionality and the dynamic power consumption characteristics of a heterogeneous processor architecture when operating in different configurations. The analysis illustrates, both qualitatively and quantitatively, that knowledge of the statistics of the incoming workload is critical to determine the appropriate processor configuration.

<p>Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well.</p><p>In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources.</p><p>In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations.</p><p>The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs.</p><p>Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.</p>

Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well. In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources. In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations. The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs. Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.

En la última década los ingenieros informáticos se han enfrentado a profundos cambios en el modo en que se diseñan y fabrican los microprocesadores. Los nuevos procesadores no solo deben ser más rápidos que los anteriores, también deben ser factibles en términos de energía y disipación térmica, sobre todo en dispositivos que trabajan con baterías. Los problemas relacionados con consumo y temperatura son muy comunes en estos procesadores. En esta Tesis analizamos el rendimiento, consumo energético y precisión de diferentes mecanismos de reducción de consumo y descubrimos que no son suficientemente buenos para adaptarse a un límite de consumo con una penalización de rendimiento razonable. Para solucionar este problema proponemos diversas técnicas a nivel de microarquitectura que combinan de manera dinámica varios mecanismos de reducción de consumo para obtener una aproximación al límite de consumo mucho más precisa con una penalización de rendimiento mínima. / In the last decade computer engineers have faced changes in the way microprocessors are designed. New microprocessors do not only need to be faster than the previous generation, but also be feasible in terms of energy consumption and thermal dissipation, especially in battery operated devices. In this Thesis we worked in the design, implementation and testing of microarchitecture techniques for accurately adapting the processor performance to power constraints in the single core scenario, multi-core scenario and 3D die-stacked core scenario. We first designed “Power-Tokens”,to approximate the power being consumed by the processor in real time. Later we proposed different mechanisms based on pipeline throttling, confidence estimation, instruction criticality information, to adapt the processor to a predefined power budget . We also propose some layout optimizations for 3D die-stacked vertical designs.