De tout temps, l’Homme s’est vu contraint de protéger les fruits de sa créativité et les domaines concernant sa sécurité. Ses informations sont souvent sensibles, dans les relations politiques et commerciales notamment. Aussi, la nécessité de les protéger en les rendant opaques au regard d’adversaires ou de concurrents est vite survenue. Depuis l’Antiquité, les procédés de masquages et enfin de cryptages furent nombreux. Les techniques de protection, depuis l’époque industrielle n’ont fait que croître pour voir apparaître, durant la seconde guerre mondiale, l’archétype des machines électromécaniques (telle l’Enigma), aux performances réputées inviolables. De nos jours, les nouveaux circuits de protection embarquent des procédés aux algorithmes hyper performants. Malgré toutes ces protections, les produits restent la cible privilégiée des « pirates » qui cherchent à casser par tous les moyens les structures de sécurisation, en vue d’utilisations frauduleuses. Ces « hackers » disposent d’une multitude de techniques d’attaques, l’une d’elles utilise un procédé par injections de fautes à l’aide d’un faisceau laser. Dès le début de ce manuscrit (Chapitre I), l’état de l’art de l’injection de fautes sera développé, en se focalisant sur celles faite à l’aide d’un faisceau laser. Ceci aidera à bien appréhender ces procédés intrusifs et ainsi protéger au mieux les microcontrôleurs sécurisés contre ces types d’attaques. Il est nécessaire de bien comprendre les phénomènes physiques mis en jeu lors de l’interaction entre une onde de lumière cohérente, tels les lasers et le matériau physico-chimique qu’est le silicium. De la compréhension de ces phénomènes, une modélisation électrique des portes CMOS sous illumination laser a été mise en oeuvre pour prévoir leurs comportements (chapitre II). De bonnes corrélations ont pu être obtenues entre mesures et simulations électrique. Ces résultats peuvent permettre de tester la sensibilité au laser de portes CMOS au travers de cartographies de simulation. De cette meilleure compréhension des phénomènes et de ce simulateur mis en place, de nombreuses contre-mesures ont été imaginées. Les nouvelles techniques développées, présentées dans ce manuscrit, donnent déjà des pistes pour accroître la robustesse des circuits CMOS contre des attaques laser. D’ores et déjà, ce travail a permis la mise en oeuvre de détecteurs lasers embarqués sur les puces récentes, renforçant ainsi sensiblement la sécurité des produits contre une attaque de type laser. / From time immemorial, human beings have been forced to protect the fruits of their creativity and ensure the security of their property. This information is very often strategic, in particular in political and commercial relationships. Also the need to protect this information by keeping it concealed in regards to enemies or competitors soon appeared. From ancient times, the methods used for masking and eventually encrypting information were numerous. Protection techniques have only advanced grown since the industrial era and have led to the precursor of electro-mechanic machines (such as the famous Enigma machine). Nowadays, new protection circuitry embeds very efficient algorithms. Despite these protections, they remain a prime target for « attackers » who try to break through all means of securing structures, for fraudulent uses. These « attackers » have a multitude of attack techniques. One of them uses a method of fault injections using a laser beam. From the beginning (Chapter I), this manuscript describes the state of the art of fault injections, focusing on those made using a laser beam. It explains these intrusive methods and provides information on how to protect even the most secure microcontrollers against these types of attacks. It is necessary to understand the physical phenomena involved in the interaction between a coherent light wave, such as lasers, and the physicochemical material that makes up a microcontroller. To better understanding these phenomena, an electrical modeling of CMOS gates under laser illumination was implemented to predict their behavior (Chapter II). Good correlations have been obtained between measurements and electrical simulation. These results can be used to test the laser sensitivity of CMOS gates through electrical cartographies. Due to the better understanding of the phenomena and the developed simulator, many countermeasures have been developed. The techniques presented in this manuscript offer new possibilities to increase the robustness of CMOS circuits against laser attacks. This work has already enabled the implementation of efficient counter-measures on embedded laser sensors and significantly enhanced product security against different laser attacks.

Solar cells constitute the most direct way of converting solar energy to electricity, and thin-film solar-cell technologies have lately been growing in importance, allowing the fabrication of less expensive modules that nonetheless have good power-conversion efficiencies. This thesis focuses on solar cells based on Cu(In,Ga)Se2, which is the thin-film technology that has shown the highest conversion efficiency to date, reaching 20.3 % on the laboratory scale. Solar modules still have some way to go to become entirely competitive with existing energy technologies, and there are two possible paths to this goal: Firstly, reducing their manufacturing costs, for instance by minimizing the material usage per module and/or by increasing the throughput of a given factory; and secondly, increasing the power output per module in other words, the module efficiency. The subject matters of this thesis are related to those two approaches. The first issue investigated is the possibility for reducing the thickness of the Cu(In,Ga)Se2 layer and compensating for lost absorption by using a ZrN back reflector. ZrN layers are fabricated by reactive sputtering and I present a method for tuning the sputtering parameters so as to obtain a back reflector with good optical, electrical and mechanical properties. The reflector layer cannot be used directly in CIGS devices, but relatively good devices can be achieved with a precursor providing a homogeneous supply of Na, the addition of a very thin sacrificial Mo layer that allows the formation of a film of MoSe2 passivating the back contact, and optionally a Ga gradient that further keeps electrons away from the back contact. The second field of study concerns the three-stage CIGS coevaporation process, which is widely used in research labs around the world and has yielded small-area cells with highest efficiencies, but has not yet made it to large scale production. My focus lies on the development and the effect of gradients in the [Ga]/[In+Ga] ratio. On the one hand, I investigate 'intrinsic' gradients (ones that form autonomously during the evaporation), and present a formation model based on the differing diffusivity of Ga and In atoms in CIGS and on the development along the quasi-binary tie line between (In,Ga)2Se3 and Cu2Se. On the other hand, I determine how the process should be designed in order to preserve 'extrinsic' gradients due to interdiffusion. Lastly, I examine the electrical effects of Ga-enhancement at the back and at the front of the absorber and of In-enhancement at the front. Over a wide range, In-rich top layers prove to have no or a weakly beneficial effect, while Ga-rich top regions pose a high risk to have a devastating effect on device performance.

Dans le domaine ferroviaire de nombreux incidents ont montré le problème de l'échauffement de la caténaire au droit du contact avec le pantographe durant le captage de courant à l'arrêt. L'échauffement à l'interface pantographe/caténaire peut entraîner la rupture du fil de contact de la caténaire. Le travail présenté dans cette étude, issu de la collaboration entre la SNCF et l'institut FEMTO-ST, vise à améliorer la compréhension des phénomènes physiques mis en jeu. L'objectif à terme est d'anticiper une maintenance coûteuse comme le remplacement du fil de contact. Un modèle électrothermique 2D transitoire du fil de contact a été développé et couplé à un modèle thermique 1D transitoire pour obtenir une modélisation quasi 3D. La modélisation, alimentée par des données expérimentales, permet de déterminer la répartition du courant électrique et donc la production de chaleur interne. Une modélisation électrothermique de la bande vient compléter le système. / In the railroad and trains domain, many incidents show the main problem of overheating of the catenary at the contact with the pantograph when the train was stopped whereas all the electrical systems of the train should nevertheless be fed. Analysis of these incidents has shown that the overheating of the interface catenary-pantograph during the ream conditioning was sometimes at the origin of the break of the contact wire. In order to forecast such very expensive problems for the company, the French National Railway Company (SNCF) and the research institute FEMTO-ST carried out theoretical and experimental studies to better understand this phenomenon. First a quasi 3D transient electrothermal modeling tool has been developed for the contact wire. It has also permitted to estimate the distribution of current in the wire in order to obtain the internal heat power generation. An electrothermal modelisation of the strip complete the system. Finally the heat transfer equation in the wire with particular boundary conditions has been solved in all the finite differences network thanks to the Euler's implicit method.

A deeper understanding of Cu(In,Ga)Se2 (CIGS) solar cells is important for the further improvement of these devices. This thesis is focused on the use of electrical modelling as a tool for pursuing this aim. Finished devices and individual layers are characterized and the acquired data are used as input in the simulations. Band gap gradients are accounted for when modelling the devices. The thesis is divided into two main parts. One part that treats the influence of cadmium free buffer layers, mainly atomic layer deposited (Zn,Mg)O, on devices and another part in which the result of CIGS absorber layer modifications is studied. Recombination analysis indicates that interface recombination is limitting the open circuit voltage (Voc) in cells with ZnO buffer layers. This recombination path becomes less important when magnesium is introduced into the ZnO giving a positive conduction band offset (CBO) towards the CIGS absorber layer. Light induced persistent photoconductivity (PPC) is demonstrated in (Zn,Mg)O thin films. Device modelling shows that the measured PPC, coupled with a high density of acceptors in the buffer-absorber interface region, can explain light induced metastable efficiency improvement in CIGS solar cells with (Zn,Mg)O buffer layers. It is shown that a thin indium rich layer closest to the buffer does not give any significant impact on the performance of devices dominated by recombination in the CIGS layer. In our cells with CdS buffer the diffusion length in the CIGS layer is the main limitting factor. A thinner CIGS layer improves Voc by reducing recombination. However, for thin enough absorber layers Voc deteriorates due to recombination at the back contact. Interface recombination is a problem in thin devices with Zn(O,S) buffer layers. This recombination path is overshadowed in cells of standard thickness by recombination in the CIGS bulk. Thin cells with Zn(O,S) buffer layers have a higher efficiency than CdS cells with the same absorber thickness.

The aim of this study is to present, compare and improve the options of power transmission for tidal current arrays. The potential to generate low or zero carbon power from the world’s tides is increasing as technology moves forward. The technically available tidal current energy resource, the resource that can be captured using existing technology, in the United Kingdom can supply a significant amount of the UK electricity demand. Even though tidal current devices have similarities to offshore wind turbines in many aspects, a number of characteristics differentiate the approach needed regarding power transmission and drive-train design. Some of these characteristics are: predictable direction and speed of the tidal current, predetermined available area in a tidal channel, less swept area due higher density of water, continuous underwater operation and smaller distances to shore. This thesis is based on the hypothesis that tidal current energy can be harnessed using today’s technology in an efficient manner. Technology progression never stops and as new materials and methods become available the cost of utilising tidal current energy will drop in the years to come. However, the research question that has to be asked is whether using today’s technology tidal arrays can be an alternative source of electrical power. In order to respond to this research question electromechanical models of tidal current devices have been developed in detail, from resource to the grid connection, using mathematical linear and non-linear programming in MATLAB/Simulink. The tidal models developed include the tidal resource, the tidal turbine with pitch control, geared induction and synchronous generators, the power electronics with the generator controller, the grid side controller, the cables for power transmission, the filters and the grid connection. All the modelling aspects of this study are presented in Chapter 3. Single tidal current devices were compared using different generator technologies, squirrel cage induction generator or permanent magnet synchronous generator, and different location of the power converters, in the nacelle near the generator or many kilometres apart from the generator. Regarding the generator technology, results showed that even though differences are minor, the permanent magnet synchronous generators are more efficient. Regarding the location of the power converters results showed that positioning the power converters in the nacelle always yields fewer electrical losses but component accessibility is minimised due to the underwater operation of the tidal current device. A key focus aspect of the study is the power transmission option with onshore converters which is presented in detail. Using this concept it is possible to generate electricity from tidal current devices but at the same time keep the highest possible system reliability despite the continuous underwater operation. This concept has been used in the first demonstration tidal current arrays developed by Andritz Hydro Hammerfest. What is more, data provided by Andritz Hydro Hammerfest were utilised in order to validate the simulation models. In this study a step forward is taken regarding the concept of keeping the converter dry and controlling the tidal current generator from afar. An algorithm is developed to design power harmonic filters for systems that use long distance controls. Power harmonic filters allow the long distance control system to operate reliably under all conditions but generate significant electrical losses. The power harmonic filter design algorithm presented in this thesis estimates the exact filter parameters so that the filter ensures maximum system reliability and generate minimum possible losses. In addition tidal array topologies using this concept are developed. The final part of this thesis compares a number of different tidal array topologies based on resource to grid efficiency and component accessibility for maintenance. Results showed that when tidal current devices are clustered per four turbines on offshore platforms it is efficient to use as many clusters as possible connected to a single cable whose both ends are connected to the grid. Locating the power converters in the nacelle yields fewer electrical losses compared to locating the power converters on the offshore platform. However, the difference is minimised because the distance between the tidal current device and the offshore platform is the least possible. Having the power converters on an offshore platform is beneficial in terms of accessibility for maintenance and operation because they are not underwater. The results and the methodology from this thesis can be extended to other offshore renewable energy systems such as the wind and wave. In addition, this study can be used as a stepping stone for decision making by tidal current developers.

Ce travail porte sur l’analyse et l’étude du comportement de circuits intégrés en technologie CMOS soumis à un impact laser. Une méthodologie d’implémentation d’un impact laser a été développée et améliorée. Ainsi, elle est applicable à n’importe quelle description électrique d’un circuit CMOS, qu’il soit digital ou analogique. Ce procédé est conçu pour permettre aux concepteurs de circuits intégrés pouvant être soumis à des attaques laser, de tester leur circuit en simulation avant leur fabrication et de démontrer leur robustesse.Notre étude s’est focalisée sur le développement d’un outil de simulation intégrant un modèle électrique de l’impact laser sur les transistors MOS afin de reproduire de façon qualitative le comportement du circuit face à un impact laser (attaque semi-invasive en face arrière du circuit), et ce quelques soient ses propriétés physiques.Une première partie d’état de l’art est consacrée à la synthèse des différentes attaques sur circuits sécurisées que l’on peut rencontrer dans le domaine de la microélectronique, telles que les attaques semi-invasives, non invasives ou invasives par exemple. Une seconde partie théorique dédiée à l’interaction laser-silicium au niveau physique nous permet d’étudier les différents acteurs mis en jeu (propriétés physiques du laser – puissance, diamètre et profil du faisceau), avant de les importer comme paramètres dans le domaine électrique.Cette étude se poursuit alors par l’élaboration d’un modèle électrique et d’une méthodologie de simulation dont le but est de permettre de reproduire le comportement de n’importe quel circuit impacté par un laser. Le flot de modélisation passe ainsi en revue l’ensemble des paramètres contrôlables en entrée, qu’il s’agisse des propriétés physiques du laser, traduites dans le domaine électrique, ou encore de la réalité géométrique du circuit impacté, quel que soit sa complexité. Par ailleurs, la flexibilité de cette approche permet de s’adapter à toute évolution du modèle de l’impact laser en lui-même. Il est ainsi possible de simuler un impact intégrant ou non tout ou partie des phénomènes parasites déclenchés par le photocourant. Enfin, il couvre aussi bien des analyses de comportement dans le domaine statique, que dans celui temporel, où la durée d’impulsion du laser prend toute son importance.Afin de démontrer la cohérence de cette méthodologie face à nos attentes théoriques, le comportement de transistors NMOS, PMOS et un inverseur CMOS ont été étudiés au niveau simulation. Cette étude préliminaire nous a permis de calibrer et de valider notre modèle et sa méthodologie d’utilisation avec la théorie attendue: création d’un photocourant proportionnel au potentiel appliqué sur la jonction de drain et couplé au potentiel photoélectrique ainsi qu’à la surface impactée, déclenchement des bipolaires parasites latéraux, etc…. L’analyse sur un inverseur CMOS bufférisé ou non nous donne encore plus d’informations quant aux analyses dynamiques ou statiques : un impact sur un état statique (0 ou 1) ne peut entraîner que des fautes fonctionnelles, alors qu’un impact sur une transition ralentit ou accélère le signal en sortie, au risque de générer une faute fonctionnelle.Enfin, l’étude de différents circuits complexes sur silicium face à plusieurs types de faisceau laser nous a permis de confronter notre méthodologie à la mesure. Une chaîne d’inverseurs, une bascule de type D, et un circuit de verrouillage ont ainsi été impactés. Les résultats observés en simulation sont cohérents avec la mesure, notamment du point de vue comportemental et fonctionnel. / This present work deals with the analysis and study of the integrated circuits behavior in CMOS technology under laser injection. An implementation methodology of a laser impact has been developed and optimized. The study has been focused on the development of a simulation tool integrating an electrical model of a laser impact on MOS transistor. This allows to reproduce in a qualitative way the behavior of a circuit under laser impact (semi-invasive attack on rear face of the circuit), whatever the physical properties of the laser.A preliminary study allowed us to calibrate a new electrical model and its use methodology based on the expected theory: photocurrent creation proportional to the applied potential on the drain junction and linked to the photoelectrical potential with the impacted area; triggering of the lateral parasitic bipolar transistors.The analysis of different complex circuits on silicon under different kind of laser beam allowed us also to validate the developed tool and its implementation methodology: it will help designers to prevent or predict such behavior of their circuits under laser attack, allowing them to find solutions of countermeasures and thus making their integrated circuits more robust in critical applications.