The median-times-to-failure (t₅₀’s) for straight dual-damascene via-terminated copper interconnect structures, tested under the same conditions, depend on whether the vias connect down to underlaying leads (metal 2, M2, or via-below structures) or connect up to overlaying leads (metal 1, M1, or via-above structures). Experimental results for a variety of line lengths, widths, and numbers of vias show higher t₅₀’s for M2 structures than for analogous M1 structures. It has been shown that despite this asymmetry in lifetimes, the electromigration drift velocity is the same for these two types of structures, suggesting that fatal void volumes are different in these two cases. A numerical simulation tool based on the Korhonen model has been developed and used to simulate the conditions for void growth and correlate fatal void sizes with lifetimes. These simulations suggest that the average fatal void size for M2 structures is more than twice the size of that of M1 structures. This result supports an earlier suggestion that preferential nucleation at the Cu/Si₃N₄ interface in both M1 and M2 structures leads to different fatal void sizes, because larger voids are required to span the line thickness in M2 structures while smaller voids at the base of vias can cause failures in M1 structures. However, it is also found that the fatal void sizes corresponding to the shortest-times-to-failure (STTF’s) are similar for M1 and M2, suggesting that the voids that lead to the shortest lifetimes occur at or in the vias in both cases, where a void need only span the via to cause failure. Correlation of lifetimes and critical void volumes provides a useful tool for distinguishing failure mechanisms. / Singapore-MIT Alliance (SMA)

Electromigration experiments have been carried out on straight interconnects that have single vias at each end, and are divided into two segments by a via in the center ("dotted-I" structures). For dotted-i structures in the second metal layer (M2) and with 25µm-long segments length, failures occurred even when the product of the current density and segment length (jL) was as low as 1250A/cm, even though via terminated 25µm-long lines are "immortal" when (jL)cr < 1500 A/cm. Moreover, we found the mortalities of the dotted-I segments to be dependent on the current density and current direction in the adjacent segment. These result suggest that there is not a definite value of jL product that defines true immortality in individual segments that are part of an interconnect tree, and that the critical value of jL for Cu dual damascene segments is dependent on the magnitude and direction of current flow in adjacent segments. Therefore, (jL)cr values determined in two-terminal via-terminated lines cannot be directly applied to interconnects with branched segments, but rather the magnitude as well as the direction of the current flow in the adjoining segments must be taken into consideration in determining the immortality of interconnect segments. / Singapore-MIT Alliance (SMA)

The plasma-based etching processes of copper (Cu) and titanium tungsten (TiW) thin films, and the electromigration of the copper lines patterned by above etching processes were studied. Instead of vaporizing the plasma/copper reaction product, a dilute hydrogen chloride solution was used to dissolve the nonvolatile reaction product. The plasma/copper reaction process was affected by many factors including the microstructure of the copper film and the plasma conditions. Under the same chlorine plasma exposure condition, the copper conversation rate and the copper chloride (CuClx) formation rate increased monotonically with the Cu grain size. The characteristics of the Cu etching process were explained by diffusion mechanisms of Cl and Cu in the plasmacopper reaction process as well as microstructures of Cu and CuClx. The Cu chlorination process was also affected by the additive gas in the Cl2 plasma. The additive gas, such as Ar, N2, and CF4, dramatically changed the plasma phase chemistry, i.e., the Cl concentration, and the ion bombardment energy, which resulted in changes of the Cu chlorination rate and the sidewall roughness. TiW thin films, used as the diffusion barrier layer for the Cu film, were reactive ion etched with CF4/O2, CF4/Cl2, and CF4/HCl plasma. Process parameter such as feed gas composition, RF power, and plasma pressure showed tremendous effects on the etch rate and the etch selectivity. The TiW etch rate was a function of the sum of Cl and F concentrations and the ion bombardment energy. Cu/diffusion barrier metal stack was successfully patterned by above plasma etch processes. The electromigration (EM) performance of the Cu lines was evaluated by the accelerated isothermal test. The activation energy of 0.5~0.6 eV and the current density exponent of 2.7 were obtained. Failure analysis showed that both copper-silicon nitride cap layer interface and the copper grain boundary were active diffusion paths. The EM induced stress caused the cap layer crack and affected the reliability of Cu lines. The processes studied in this dissertation can be applied in advanced microelectronic fabrication including large area flexible microelectronics.

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Failure mechanisms observed in electromigration (EM) stressed dual damascene Cu/SiO₂ interconnects trees were studied and simulated. Failure sites with ‘melt patch’ or ‘crater’ are common for test structures in the top metal layer, though the occurrence of such failure modes probably depends on the passivation layer thickness. Interconnects that were EM stressed for a short time and then stressed with increasing current to induce Joule heating in the line had similar failure sites to lines that were stressed to failure under standard EM conditions. This shows that some failure mechanisms during EM could be assisted by Joule heating effect. / Singapore-MIT Alliance (SMA)

The effect of electromigration on void formation and the failure mechanism of FCBGA packages under a current density of 1*104 A/cm2 and an environmental temperature of 150¢J was investigated. Eight solder/substrate combinations of four lead-free solder systems with two substrates were examined to verify the failure modes. A conservative failure criterion was adopted to define and predict the failure of the package. SEM was employed to observe in situ microstructural changes, IMC growth, and failure modes. All samples exhibited a similar failure, attributed mainly to void occupation along UBM/solder interfaces at the cathode chip side of the bumps with downward electron flow. Voids were initiated at the corner due to current crowding. Two specific void locations were identified at the IMC/solder and UBM/IMC interfaces, and they co-existed in the same specimen but in different bumps. No void coupling mode was found. Since the atom diffusion rate in the solder differs from that in the IMC layer, the voids can be formed between them. A current density of 1*104 A/cm2 was sufficiently high to form a void pattern at the IMC/solder interface. However, the formation of voids at the UBM/IMC interface is generally induced by the consumption of UBM, since the high temperature of 150¢J crucially dominates the void morphology at the UBM/IMC interface. The difference among solder systems did not affect the failure modes nor dominate mechanisms. Two theoretical models based on the experimental results were applied to describe the void formations. They will be more accurate and useful in understanding void formations by further experimental data provided. According to the results of solder bumps with electrons only flowed through Al trace line at die side, it suggested that atoms transport toward the bottom substrate along with the temperature gradient and toward the right corners along with electron flow when electrons flowed through the trace after the resistances of solder joints reaching 120¢H of their initial values. With respect to the differences of substrate surface finishes, more voids appeared at the cathode substrate side of the solders combined with Cu/Ni/Au pad than those combined with Cu-OSP after long-term upward electron stressing. It suggested another possible failure at the substrate side when failure did not occur at the chip side in an EM test.

Electromigration (EM) describes the mass transport in a metal driven by the momentum transfer from electron scattering with metal ions. This can develop into a degradation process due to void growth for on-chip interconnects when subjected to high electric current densities and eventual interconnect line failure. The mass transport occurs in decreasing order of magnitude along interfaces grain boundaries and in bulk. The diffusivities along interfaces and grain boundaries are determined by crystallographic orientation. Diffusion discontinuities can create flux divergent sites that control void growth kinetics and failure characteristics. Most of the earlier studies of EM modeling have assumed an averaged diffusivity measured across the underlying crystallographic microstructure. The objective of this thesis is to study the effect of microstructure on EM reliability by modeling of the diffusivity corresponding to grain orientation at the interface and to project the EM lifetime and the standard deviation (sigma) of the failure statistics. The simulation consists of two parts. First, the microstructure is generated using a Monte Carlo algorithm based on the Potts model. In the second stage, the void formation and growth induced by electromigration is modeled until a maximum time elapsed. During the void growth, the electrical resistance is monitored to search for EM failure subjected to a 400% (5 times the initial value) resistance increase failure criterion. The simulated electromigration lifetimes were found to follow a log-normal distribution. The computations were carried out on a parallel computer, simulating a population of 100 interconnect segments with random microstructure configurations. In this way, the 100 interconnect segments form the basis for statistical analysis of a special simulation run. Simulation runs were carried out with microstructures varying over a range of grain sizes and diffusivity for the top interface. In the simulation, four cases were studied and compared to results from EM experiments. These four cases were large and small grains combined with slow and fast diffusing top interfaces. Results from the simulation revealed a consistent trend in that large grains prolong the electromigration lifetime, especially for the case of a slow diffusing top interface. This trend is also consistent with the experimental results where the lifetime was found to increase in the order of small grain/fast interface, large grain/fast interface, small grain/slow interface and large grain/slow interface. The overall agreement, however, is only qualitative. For instance, the EM experiment showed a lifetime improvement of more than 100 fold whereas the simulation only showed an improvement of 6 fold from fast to slow interface for large grains. / text

First proposed in the late 1990's, a nanomechanical electron shuttle is a device where an electrically isolated island moves a definite number of electrons between two leads, producing a current that is directly related to the number of electrons moved in a cycle and to the vibration frequency of the island. Since nanomechanical structures can have very well defined vibration frequencies, a device of this type is useful as, among other things, a current standard for metrology. The experimental shuttle implementations to date have had large island-lead spacings, which has limited their performance. The work presented here takes the first steps towards the fabrication of a nanomechanical electron shuttle using the process of electromigration to define very small lead-island gaps with conductivity on the order of the conductance quantum G_0=2e^2/h. These small gaps, coupled with the high vibration frequencies achievable with nanostructures, will allow investigation deeper into the realm of quantum effects. In this work, the fabrication steps for the creation of these devices were developed. Electromigration of a single junction was successfully achieved to the 10--100\,k\ohm range. The simultaneous and symmetric electromigration of two junctions, as required for the shuttle, has not yet been achieved. The development of a fast electromigration cut-off circuit, however, gives hope that double-breaking success will be achieved soon. / Thesis (Master, Physics, Engineering Physics and Astronomy) -- Queen's University, 2010-01-28 23:01:15.735

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As the trend of miniaturization of complex integrated circuit(IC) devices, the current density of flip-chip solder bumps have increased significantly and each solder joint is supporting a current density close to or even over 104 A/cm2 .Therefore, in SnPb eutectic solder, which has a high diffusivity at the operating temperature due to its low melting point, the electromigration becomes a major reliability threat. Thus, the thesis is aimed to investigate the effects of electromigration behavior on flip-chip package eutectic Sn-Pb solder bumps reliability under high current density. The current densities are 2x104 A/cm2 and 1.5x104 A/cm2,the surface of die temperatures are 115¢Jand 95¢J.The bump temperature, the histories of the bump resistance, and mean time to failure (MTTF) testings were conducted. The failure mechanism was observed through SEM and EDS. From the results of the experiment, the dominant failure mode of the bump is due to electromigration behavior that causes voids at UBM/bump interface (cathode) when the sample¡¦s failure time is shorter. As the failure time is longer, the failure is also resulted from heat effect in addition to electromigration behavior.