Electromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional area of interconnects can degrade the EM-related lifetime of IC, which is expected to become more severe in future technology nodes. Moreover, as EM is governed by various factors such as temperature, material property, geometrical shape, and mechanical stress, different interconnect structures can have distinct EM issues and solutions to mitigate them. For example, one of the most prominent technologies, die stacking technology of three-dimensional (3D) ICs, can have different EM problems from that of planer ICs, due to their unique interconnects such as through-silicon vias (TSVs). This dissertation investigates EM in various interconnect structures, and applies the EM models to optimize IC layout. First, modeling of EM is developed for chip-level interconnects, such as wires, local vias, TSVs, and multi-scale vias (MSVs). Based on the models, fast and accurate EM-prediction methods are proposed for the chip-level designs. After that, by utilizing the EM-prediction methods, the layout optimization methods are suggested, such as EM-aware routing for 3D ICs and EM-aware redundant via insertion for the future technology nodes in VLSI. Experimental results show that the proposed EM modeling approaches enable fast and accurate EM evaluation for chip design, and the EM-aware layout optimization methods improve EM-robustness of advanced VLSI designs. / text

Electromigration (EM) remains a major reliability concern for on-chip Cu interconnects due to the continuing scaling and the introduction of new materials and processes. In Cu interconnects, the atomic diffusion along the Cu/SiCN cap interface dominates the mass transport and thus controls EM reliability. The EM lifetime degrades by half for each new generation due to the scaling of the critical void volume which induces the EM failure. To improve the EM performance, a metal cap such as CoWP was applied to the Cu surface to suppress the interfacial diffusion. By this approach, two orders of magnitude improvement in the EM lifetime was demonstrated. For Cu lines narrower than 90 nm, the Cu grain structure degraded from bamboo-like grains to polycrystalline grains due to the insufficient grain growth in the trench. Such a change in Cu grain structures can increase the mass transport through grain boundaries and thus degrade the EM performance. The objective of this study is to investigate the scaling effect on EM lifetime and Cu microstructure, and more importantly, the grain structure effect on EM behaviors of Cu interconnects with the CoWP cap compared to those with the SiCN cap only. This thesis is organized into three parts. In the first part, the effect of via scaling on EM reliability was studied by examining two types of specially designed test structures. The EM lifetime degraded with the via size scaling because the critical void size that causes the EM failure is the same with the via size. The line scaling effect on Cu grain structures were identified by examining Cu lines down to 60 nm in width using both plan-view and cross-sectional view transmission electron microscopy. In the second part, the effect of grain structure was investigated by examining the EM lifetime, statistics and failure modes for Cu interconnects with different caps. A more significant effect of the grain structure on EM characteristics was observed for the CoWP cap compared to the SiCN cap. For the CoWP cap, the grain structure not only affected the mass transport rate along the Cu line, but also impacted the flux divergence site distribution which determined the voiding location and the lifetime statistics. Finally, the effect of grain structure on EM characteristics of CoWP capped Cu interconnects was examined using a microstructure-based statistical model. In this model, the microstructure of Cu interconnects was simplified as cluster and bamboo grains connected in series. Based on the weakest-link approximation, it was shown that the EM lifetime and statistics could be adequately modeled by combining the measured cluster length distribution with the EM lifetime-cluster length correlation for each individual failure unit. / text

Electromigration is re-emerging as a significant problem in modern integrated circuits (IC). Especially in power-grids, due to shrinking wire widths and increasing current densities, there is little or no margin left between the predicted EM stress and that allowed by the EM design rules. Statistical Electromigration Budgeting estimates the reliability of the grid by considering it as a series system. However, a power grid with its many parallel paths has much inherent redundancy. In this work, we propose a new model to estimate the MTF and reliability of the power grid under the influence of EM, which accounts for these redundancies. To implement the mesh model, we also develop a framework to estimate the change in statistics of an interconnect as its effective-EM current varies. The results indicate that the series model gives a pessimistic estimate of power grid MTF by a factor of 3-4.

Electromigration in metal lines has re-emerged as a significant concern in modern VLSI circuits. The higher levels of temperature and the large number of EM checking strategies, have led to a situation where trying to guarantee EM reliability often leads to conservative designs that may not meet the area or performance specs. Due to their mostly-unidirectional currents, the problem is most significant in power grids. Thus, this work is aimed at reducing the pessimism in EM prediction. There are two sources for the pessimism: the use of the series model for EM checking, and the pessimistic assumptions about chip workload. Therefore, we propose an EM checking framework that allows users to specify conditions-of-use type constraints to capture realistic chip workload, and which includes the use of a novel mesh model for EM prediction in the grid, instead of the traditional series model.

Electromigration is re-emerging as a significant problem in modern integrated circuits (IC). Especially in power-grids, due to shrinking wire widths and increasing current densities, there is little or no margin left between the predicted EM stress and that allowed by the EM design rules. Statistical Electromigration Budgeting estimates the reliability of the grid by considering it as a series system. However, a power grid with its many parallel paths has much inherent redundancy. In this work, we propose a new model to estimate the MTF and reliability of the power grid under the influence of EM, which accounts for these redundancies. To implement the mesh model, we also develop a framework to estimate the change in statistics of an interconnect as its effective-EM current varies. The results indicate that the series model gives a pessimistic estimate of power grid MTF by a factor of 3-4.

Electromigration in metal lines has re-emerged as a significant concern in modern VLSI circuits. The higher levels of temperature and the large number of EM checking strategies, have led to a situation where trying to guarantee EM reliability often leads to conservative designs that may not meet the area or performance specs. Due to their mostly-unidirectional currents, the problem is most significant in power grids. Thus, this work is aimed at reducing the pessimism in EM prediction. There are two sources for the pessimism: the use of the series model for EM checking, and the pessimistic assumptions about chip workload. Therefore, we propose an EM checking framework that allows users to specify conditions-of-use type constraints to capture realistic chip workload, and which includes the use of a novel mesh model for EM prediction in the grid, instead of the traditional series model.

With the constant scaling of semiconductor devices, reliability of these devices is a huge concern. One of the biggest reliability issues is a phenomenon known as electromigration (EM) [1] [2]. Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms [27]. The damage induced by electromigration appears as the formation of voids and hillocks, resulting in electrical discontinuity. Based on previous Electromigration research [15], I have created a tool chain that identifies where electromigration is likely to occur in large-scale integrated circuits. Using this tool chain, it is possible to identify the mean-time to failure (MTTF) of several common and high priority circuits such as complex adders and memories. Furthermore, this tool chain allows designers to isolate weak-points in these circuits to improve the overall MTTF of the circuit. The result is that with a few simple changes, circuits can be redesigned to increase the MTTF, at minimal cost to the system.

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L'electromigration est identifiée comme la principale cause de dégradation des interconnexions en cuivre limitant ainsi la fiabilité des produits issus de la microélectronique. Dans ces travaux nous proposons d'approfondir notre connaissance de ce phénomène en étudiant le lien qu'il présente avec les paramètres morphologiques du cuivre. Dans ce but, la technique de diffraction des électrons rétrodiffusés est utilisée. Nous avons d'abord développé les méthodes de préparation et d'acquisition nécessaires afin de pouvoir caractériser les structures issues des technologies 45 nm et au-delà que nous avons choisies pour cette étude. Un lien entre les joints de grains de forte désorientation et la localisation des cavités a alors pu être mis en évidence. Nous avons ensuite tenté de modifier la microstructure du cuivre pour impacter la fiabilité sans succès. Finalement, c'est l'intégration de nouveaux matériaux (Al, Co) renforçant l'interface supérieure, chemin de diffusion du phénomène, qui semble être la voie à adopter pour améliorer la résistance des lignes à l'électromigration. / Electromigration is one of the major cause of copper interconnect degradation which limits reliability of microelectronic products. In these works, link between copper morphological parameters and electromigration is studied to get more knowledge of this phenomenon. For that, copper structures from 45 nm technology node and beyond are characterized by backscattered electron diffraction technique. In a first time, developments of sample preparation and acquisition methodology are performed to be able to characterize small dimensions structures from technology node chosen. A link between high angle grain boundary and void location has been highlighted. Then we tried to improve reliability by copper microstructure change without success. It seems that right way to improve interconnect resistance toward electromigration is the introduction of new materials in copper (Al, Co) to reinforce upper interface which is critical diffusion path of electromigration phenomenon.

L'électromigration (EMG) est l'une des conséquences de la course à la miniaturisation des composants électroniques en général et la réduction des dimensions des interconnexions en particulier. Il est identifié comme l'un des phénomènes critiques de fiabilité pour les circuits intégrés en technologies submicroniques. Les méthodes de vérification de ce phénomène utilisées durant la conception de circuits sont pour la plupart basées sur des règles de densité de courants et de température. Ces règles deviennent de plus en plus difficiles à mettre en place, compte tenue de l'augmentation des densités de courant dans les réseaux d'interconnexions. Les travaux de cette thèse s'inscrivent dans la dynamique de recherches de moyens d'amélioration de la détection des risques d'électromigration durant la phase de conception. Le but est d'établir une relation entre violations des règles électriques et la physique de dégradation des interconnexions. Les résultats obtenus au cours des tests de vieillissement nous ont permis de repousser les limites de courant sans altérer les durées de vie des circuits. Enfin, ce projet été l'occasion de définir des règles conception basé sur l'optimisation des cellules d'horloges dans la grille d'alimentation des circuits intégrés. L'application des solutions proposées au cours de ces travaux ont permis de réaliser des circuits robustes aux effets EMG. / Electromigration (EMG) is a consequence of miniaturization of integrated circuits in general and the reduction of interconnect dimensions in particular. It is identified as one of the critical reliability phenomenon for integrated circuits designed in submicron technologies. The methods of checking this phenomenon at design level are mostly based on current density rules and temperature. These rules are becoming difficult to implement due to increasing current density in interconnection network. This thesis is based on researching for ways to improve detection of electromigration risks at design level. The goal is to establish a relation between electrical rules and interconnect degradation mechanism. Results obtained from ageing tests permit us to relax current limit without altered circuit lifetimes. Finally, this project has been instrumental to define design rules based on optimization of clock tree cells placement in integrated circuit power grid. The application of solution proposed during this work permit to design robust circuits toward EMG.