These thesis deals with electromigration in solder joint. In theoretical part are described lead-free solders, surface finish, formation of solder joint, intermetallic compounds a electromigration. In practical part is investigated a effect of electromigration on growth intermetallic compounds in solder jsoint.

Diploma thesis introduces the problems of electromigration, fluxes and flux residues. It includes a proposal for methods of measuring surface insulation resistance, information about selected types of fluxes and conformal coatings. It focuses on the influence of temperature, humidity. There are applied conductometric method and method of measuring SIR by IPC-25-B. The thesis describes the practical measurement of SIR and ionic contamination of PCB covered with flux and influence of RH, temperature and applied voltage is evaluated and discussed.

Aufgrund von guten Eigenschaften als Kupferdiffusionsbarriere und guter elektrischer Leitfähigkeit könnte sich Ruthenium und Ruthenium basierte Legierungen als Kupferdiffusionsbarriere eignen. Auf eine theoretische Aufarbeitung von Elektromigrationsmechanismen und in der Praxis eingesetzte Elektromigrationsteststrukturen folgen beschleunigte elektrische Elektromigrationstestergebnisse. Es konnte gezeigt werden, dass das System Kupfer, Ruthenium, Tantalnitrid Elektromigrationsstabiler als das konventionelle System Kupfer, Tantal, Tantalnitrid ist.:1 Einleitung 1 2 Stand der Forschung 2 2.1 Migrationsarten 2 2.2 Praktische Formulierung des Mechanismus der Elektromigration 2 2.3 Transportpfade der Elektromigration 3 2.4 Einflüsse auf die Elektromigration 4 2.4.1 Übersicht 4 2.4.2 Quereinfluss des mechanischen Stresses (Blech-Effekt) 5 2.4.3 Quereinfluss durch thermisch induziertem Stress 6 2.4.4 Materialwanderung aufgrund eines Temperaturgradienten 8 2.4.5 Einfluss des Leiterbahnmaterials (Legierung) 8 2.4.6 Einflüsse der Mikrostruktur 8 2.4.7 Einflüsse der Passivierung der Leiterbahnen 9 3 Theoretische Untersuchungen 9 3.1 Untersuchte Elektromigrationsteststrukturen 9 3.1.1 NIST-Struktur 9 3.1.2 Untersuchungen mithilfe der NIST-Struktur 10 3.1.3 Schlitz-Struktur 11 3.1.4 Bestimmung des Flächenwiderstandes RF = r=A der Schlitz-Struktur 12 3.1.5 Schlitzlängenänderungsgeschwindigkeit der Schlitz-Struktur 13 3.1.6 Prinzipielles Vorgehen zur Bestimmung der Schlitzlängenänderungsgeschwindigkeit als Kriterium für Elektromigrationsbeständigkeit 14 3.1.7 Blech-Struktur 15 3.1.8 Untersuchungen mithilfe der Blechstruktur 16 3.2 Vergleich der untersuchten Elektromigrationsteststrukturen 16 4 Experimentelle Untersuchungen 17 4.1 Beschreibung des Versuchsaufbaus 17 4.2 Evaluation der Messvorraussetzungen 18 4.2.1 Temperaturbeständigkeit der Messanordnungen 18 4.2.2 Oxidationsbeständigkeit der Schlitz- & Blechstruktur 19 4.2.3 Vernachlässigung Kupfer- und Leitungswiderstände 21 II 4.2.4 Untersuchungen bei verschiedenen Stromdichten (Schlitzstruktur) 22 4.2.5 Evaluation der günstigsten Schlitzlänge für Klassifikationstests 24 4.3 Untersuchungen an der NIST-Struktur 26 4.3.1 Ergebnisse 26 4.3.2 Probleme beim Versuchsaufbau und mögliche Lösungen 27 4.4 Untersuchungen an der Schlitz-Struktur 28 4.4.1 Bestimmung des Flächenwiderstands RF 28 4.4.2 Bestimmung der Schlitzlängenänderungsgeschwindigkeit 28 4.4.3 Optische Probenauswertung mittels TEM und FIB-Schnitt 30 4.4.4 Vergleich von Ta mit Ru und Ru0;95Mn0;05 31 4.4.5 Probleme beim Messaufbau und mögliche Lösungen 31 4.5 Untersuchungen an der Blechstruktur 33 4.5.1 Untersuchungen bei verschiedenen Stromdichten 33 4.5.2 Untersuchung bei verschiedenen Temperaturen 35 4.5.3 Probleme bei den Messungen und mögliche Lösungen 36 5 Zusammenfassung 37 6 Literaturverzeichnis 38

This dissertation constitutes two major sections. In the first major section, a kinetic analysis was established to investigate the electromigration (EM), enhanced intermetallic compound (IMC) growth and void formation for Sn-based Pb-free solder joints to Cu under bump metallization (UBM). The model takes into account the interfacial intermetallic reaction, Cu-Sn interdiffusion, and current stressing. A new approach was developed to derive atomic diffusivities and effective charge numbers based on Simulated Annealing (SA) in conjunction with the kinetic model. The finite difference (FD) kinetic model based on this approach accurately predicted the intermetallic compound growth when compared to empirical observation. The ultimate electromigration failure of the solder joints was caused by extensive void formation at the intermetallic interface. The void formation mechanism was analyzed by modeling the vacancy transport under electromigration. The effects of current density and Cu diffusivity in Sn solder were also investigated with the kinetic model. The second major section describes the integration of Step and Flash Imprint Lithography (S-FIL®) into an industry standard Cu/low-k dual damascene process. The yield on a Back End Of the Line (BEOL) test vehicle that contains standard test structures such as via chains with 120 nm vias was established by electrical tests. S-FIL shows promise as a cost effective solution to patterning sub 45 nm features and is capable of simultaneously patterning two levels of interconnect structures, which provides a low cost BEOL process. The critical processing step in the integration is the reactive ion etching (RIE) process that transfers the multilevel patterns to the inter-level dielectrics (ILD). An in-situ, multistep etch process was developed that gives excellent pattern structures in two industry standard Chemical Vapor Deposited (CVD) low-k dielectrics. The etch process showed excellent pattern fidelity and a wide process window. Electrical testing was conducted on the test vehicle to show that this process renders high yield and consistent via resistance. Discussions of the failure behaviors that are characteristic to the use of S-FIL are provided. / text

Evaluating data in capillary zone electrophoresis usually involves many steps that require using several different programmes. Apart from evaluating the electrophoreogram itself, it is usual to process the obtained data in some other way. For example, a suitable model is fit to the data in order to obtain physical and chemical parameters of the separation (e.g. stability constant in case of complexation). It is also important to know the accuracy of the evaluation (the calculation error). In this work, new parts of the Eval programme, originally developed for electrophoreogram evaluation, were implemented. The programme now automatically estimates the Haarhoff-van der Linde function (solution of continuity equation in capillary) parameters for analyte peak. Complexing agents are often used to improve the separation in the capillary zone electrophoresis. Complexation in the capillary can be described by its physical and chemical parameters. A new part was added to the Eval programme that allows the user to fit a rectangular hyperbole function to the obtained data. Thus, the regression parameters of this dependence can be gained. The programme can also draw profile diagrams for these parameters, from which the confidence intervals can be read. An option that allows two dependencies to be fitted at...

Martina Riesová Abstract of Ph.D. Thesis Capillary electrophoresis is a method of choice in many analytical laboratories for its high separation efficiency, rapidity, low consumption of chemicals and therefore low costs. Inherent to each electrophoretic separation system are system peaks, which can significantly affect or confuse the electrophoretic results. In capillary zone electrophoresis, position of system zones can be predicted easily and reliably by means of prediction software based on a theoretical description of electromigration. However, the prediction of only position of a system zone may not be sufficient for identification of system peaks in obtained electropherograms. Therefore, an existing theoretical model was significantly extended and new version of PeakMaster software (PeakMaster 5.3) was introduced in the framework of this thesis. PeakMaster 5.3 enables to predict not only the positions of system zones, but also their shapes and polarity. Thus, PeakMaster 5.3 improves the prediction possibility of overlapping or interaction of system peaks with analyte peaks. Moreover, composition of the sample can be optimized in order to obtain convenient shapes and amplitudes of system peaks. The applicability of capillary zone electrophoresis can be extended by addition of a complexation agent into...

Cette These experimentale examine le transport par effet tunnel entre deux couches ferromagnetiques separees par une barriere isolante ultrafine. L'enjeu de ces travaux est de rapprocher la comprehension theorique, basee sur des systemes ideaux, de la realite experimentale domin´ee par des jonctions comprenant une barriere amorphe. Au moyen de jonctions partiellement ou entierement epitaxiees integrant le materiau La0:7Sr0:3MnO3 dont nous avons confirme la polarisation de spin tunnel quasi-totale, l'influence de la structure electronique de materiaux isolants tels que SrTiO3, Ce0:69La0:31O1:845, TiO2, MgO (epitaxies) et Al2O3 (amorphe) sur le magnetotransport tunnel est mise en evidence. La theorie soutendant ces resultats est testee au moyen de mesures XMCD effectuees sur des barrieres de Al2O3 et MgO. La demi-metallicite de La0:7Sr0:3MnO3 est ensuite utilisee dans des jonctions La0:7Sr0:3MnO3 /SrTiO3 /La0:7Sr0:3MnO3 et La0:7Sr0:3MnO3 /SrTiO3 /Co afin d'affirmer quantitativement le caractere spectroscopique du transport tunnel polarise en spin entre electrodes ferromagnetiques. Ces etudes en tension montrent l'influence de la generation d'ondes de spin lors du transport tunnel sur l'ordre ferromagnetique de l'interface manganate/ isolant proche de sa temperature de transition metal-isolant. Enfin, nous utilisons l'electromigration aux interfaces afin de modifier la densite d'etats et le profil de potentiel des interfaces. Nous montrons comment il est possible de r´ealiser un dispositif aux proprietes de magnetotransport bistables; et nous examinons dans le regime tunnel Fowler-Nordheim les repercussions de ces modifications sur la formation d'etats quantifies au sein de la barriere, et l'evolution du couplage d'echange indirect entre les electrodes ferromagnetiques.

The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks. In the first work, a clock synthesis algorithm is developed for low-power and low-slew 3D clock network design. The impact of various design parameters on clock performance, including the wirelength, clock power, clock slew, and skew, is investigated. These parameters cover the TSV count, TSV parasitics, the maximum loading capacitance of the clock buffers, and the supply voltage. In the second work, a clock synthesis algorithm is developed to construct 3D clock networks for both pre-bond testability and post-bond operability. Pre-bond testing of 3D stacked ICs involves testing each individual die before bonding, which can improve the overall yield of 3D ICs by avoiding stacking defective dies with good ones. Two key techniques including TSV-buffer insertion and redundant tree generation are implemented to minimize clock skew and ensure pre-bond testing. The impact of TSV utilization and TSV parasitics on clock power is also investigated. In the third work, an obstacle-aware clock tree synthesis method is presented for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. These TSVs may occupy silicon area or routing layers. The generated clock tree does not sacrifice wirelength or clock power too much and avoids TSV-induced obstacles. In the fourth work, a decision-tree-based clock synthesis (DTCS) method is developed for low-power 3D clock network design, where TSVs form a regular 2D array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. The DTCS method explores the entire solution space for the best TSV array utilization in terms of low power. Close-to-optimal solutions can be found for power efficiency with skew minimization in short runtime. In the fifth work, current crowding and its impact on 3D power grid integrity is investigated. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. The current density distribution within a TSV and its connections to the global power grid is explored. A simple TSV model is implemented to obtain current density distributions within a TSV and its local environment. This model is checked for accuracy by comparing with identical models simulated using finite element modeling methods. The simple TSV models are integrated with the global power wires for detailed chip-scale power analysis. In the sixth work, a comprehensive multi-physics modeling approach is developed to analyze electromigration (EM) in TSV-based 3D connections. Since a TSV has regions of high current density, grain boundaries play a significant role in EM dominating atomic transport. The transient analysis is performed on atomic transport including grain and grain boundary structures. The evolution of atomic depletion and accumulation is simulated due to current crowding. And the TSV resistance change is modeled.

The increasing clock speed and the further reduction of the feature size in integrated circuits lead to increasing demands on the interconnecting material. Thus an increasing need for a metallization with low electrical resistance and high electromigration endurance exist. Copper can be count as a material with these properties. Since 1998 Copper interconnections are commercially manufactured for integrated circuits. Electromigration is the most lifetime limiting factor in modern integrated circuits. The main the electromigration behavior influencing parameter and especially the influence of the microstructure is unknown. In this work the influence of the grain boundaries and their properties on the electromigration is examined at sputtered (PVD) and electroplated (ECD) Copper interconnects. For this investigation microstructure mappings produced by electron backscatter diffraction (EBSD) are correlated to in-situ electromigration experiments inside the SEM to research the electromigration behavior and the diffusion paths. Microstructure analysis shows big a difference between the two investigated types of interconnects. In both a strong <111> fibre texture is observed, but the PVD Copper shows a stronger texture than the electroplated one. The texture index of the PVD interconnects is 15,9 whereas the ECD lines show an index of 3,9. The frequency densities of the grain boundary misorientation, which is important for the electromigration behavior, are very different for both films. The ECD lines show a fraction of 55% Sigma 3 twin boundaries and 40% high angle grain boundaries. In contrast the PVD interconnects show a fraction of 5% Sigma 3 twin boundaries, 75% high angle grain boundaries and 20% small angle grain boundaries. This shows that a reduction of the high angle grain boundaries is not related to a strong <111> fibre texture. With in-situ experiments correlated to microstructure analysis it is shown, that voiding at high angle grain boundaries occur in the down wind of blocking grains or sites where only Sigma 3 twin boundaries are present. Hillocks were formed at high angle grain boundaries in the upwind of blocking grains or sites where only small angle grain boundaries or Sigma 3 twin boundaries are found. By a statistical evaluation of the in-situ experiments it is shown that more than 50% of the observed electromigration damages could be ascribed clearly to a grain boundary related local mass flux divergence. At strings of high angle grain boundaries voiding at the cathode side and hillock growth at the anode side is shown. The distance between these voids and hillocks is always higher than the Blech length. As the current density increases the distance between these voids and hillocks decreases according to Blech´s law, whereby it´s valid for local divergence is shown. FIB cuts show, that hillocks on PVD lines grow non-epitaxial in contrast to hillocks on ECD lines, which show epitaxial growth. These differences of hillock´s growth may suggest different underlying growth mechanisms. Reliability testing performed on PVD Copper interconnects lead to an activation energy for electromigration of 0,77eV ± 0,07eV. The confidence interval includes reported values for surface and also grain boundary diffusion. This indicates that the electromigration in these experiments is mainly influenced by surface and grain boundary diffusion. In this work the nucleation of voids and hillocks related to the previous analysed microstructure is observed inside the SEM and correlated to high angle grain boundaries and their misorientation angle. The result of this work show that electromigration damage in Copper interconnects is mostly caused by inhomogeneities of the microstructure. In this process the high angle grain boundaries are the main diffusion path. / Mit steigender Taktrate u. weiter fortschreitender Integrationsdichte in mikroelektr. Schaltungen nehmen d. Anforderungen an d. Metallisierungsmaterial weiter zu. Es besteht d. zunehmende Forderung nach Metallisierungen mit geringem elektrischen Widerstand u. hoher Elektromigra- tionsfestigkeit. Kupfer kann als Material angesehen werden, welches d. Anforderungen erfüllt. Seit 1998 wird Kupfer als Metallisierungsmaterial in höchstintegr. Schaltun- gen eingesetzt. Die Elektromigration (EM) ist der d. Zuver- lässigkeit am meisten begrenzende Faktor in mod. mikro- elektron. Schaltungen. Die Haupteinflußgrößen auf d. Elektromigrationsverhalten u. insbes. d. Einfluß d. Gefüges ist unklar. In d. Arbeit wird an nichtpassivier- ten physikalisch (PVD) u. galvanisch (ECD) abgeschied. Kupferleitbahnen d. Einfluß d. Korngrenzen u. deren Eigenschaften auf d. Elektromigrationsverhalten untersucht. Dazu werden Gefügeanalysen mittels Kikuchi-Rückstreutechnik u. in-situ Elektromigrationsexperimente im Rasterelektron- enmikroskop gekoppelt, um d. Elektromigrationsverhalten u. d. Migrationspfade zu erforschen. Gefügeuntersuchungen zeigen, daß d. untersuchten Leitbahnen sich in ihren Gefügeeigenschaften deutl. unterscheiden. Beide Schichten zeigen e. <111> Fasertextur, wobei d. PVD-Leitbahnen e. deutl. schärfere Textur mit e. Texturfaktor von 15,9 gegenüber den ECD-Leitbahnen d. e. Texturfaktor von 3,9 aufweisen. Die Häufigkeitsverteilungen d. Korngrenz- Misorientierung, sind für d. beiden Schichten unterschiedl. Die ECD-Leitbahnen zeigen e. Anteil von 55% Sigma 3-Korngrenzen und 40% Großwinkelkorngrenzen. Die PVD- Leitbahnen hingegen weisen nur e. Anteil von 5% Sigma 3-Korngrenzen, 75% Großwinkelkorngrenzen u. 20% Kleinwin- kelkorngrenzen auf. Dadurch wird gezeigt, daß e. scharfe <111> Textur keine Reduzierung d. Großwinkelkorngrenzen zur Folge haben muß. Anhand von in-situ Experimenten gekoppelt mit Gefügeanalysen wird gezeigt, daß Porenbildung an Groß- winkelkorngrenzen hinter blockierenden Körnern oder hinter Bereichen auftritt, in d. nur Sigma 3-Korngrenzen o. Kleinwinkelkorngrenzen vorliegen. Hügelbildung tritt an Großwinkelkorngrenzen vor blockierenden Körnern o. Berei- chen auf, in denen nur Kleinwinkelkorngrenzen o. Sigma 3-Korngrenzen vorliegen. Mit e. statist. Auswertung d. in-situ Experimente wird gezeigt, daß mehr als d. Hälfte aller Elektromigrationsschädigungen bei beiden Herstellungsmethoden eindeutig auf e. korngrenzbedingte lokale Divergenz im Massenfluß zurückzuführen sind. An Ketten von Großwinkelkorngrenzen wird verdeutl., daß kathodenseitig Porenbildung und anodenseitig Hügelbildung auftritt. Der Abstand zw. Pore u. Hügel liegt hier immer oberh. d. Blechlänge. Mit zunehmender Stromdichte nimmt d. Pore-Hügel-Abstand entspr. d. Blechtheorie ab, wodurch gezeigt wird, daß d. Blechtheorie auch bei lokalen Flußdivergenzen gilt. FIB-Querschnittsanalysen zeigen, daß Hügel auf PVD-Leitbahnen nicht epitaktisch mit d. darunterliegenden Schicht verwachsen sind im Gegensatz zu Hügeln auf ECD-Leitbahnen, die teilw. e. epitaktische Verwachsung mit d. Leitbahn zeigen. Lebensdauermessungen an PVD-Leitbahnen ergeben e. Aktivierungsenergie von 0,77eV ± 0,07eV. Es ist davon auszugehen, daß das Elektromigrationsverhalten d. hier untersuchten unpassi- vierten Leitbahnen haupts. von Korngrenz- u. von Oberfläch- endiffusion beeinflußt wird. In d. Arbeit wurde zum ersten Mal an Kupferleitbahnen d. Entstehung von eit- bahnschädigungen im Zusammenhang mit dem vorher aufgenomme- nen Gefüge im Rasterelektronenmikroskop direkt beobachtet u. mit d. Korngrenzen u. d. Korngrenzwinkeln in Zusammenhang gebracht. Die Ergebnisse d. Arbeit zeigen, daß Schädigungen durch Elektromigration in Kupferleitbahnen vorw. durch Gefügeinhomogenitäten entstehen. Bei d. Prozeß sind Großwinkelkorngrenzen d. bevorzugte Diffusionspfad.

The continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes. / text