Les techniques d'évaluation de la composition tissulaire permettent de mieux comprendre les processus physiologiques et leur impact global sur l'état biologique des sujets expérimentaux. Le travail présenté dans ce manuscrit vise à concevoir un système de mesure intégré de spectroscopie de bioimpédance capable de mesurer un large champ de biomarqueurs sur de longues périodes (jusqu'à un an). Le système de mesure présenté peut être utilisé pour des applications de suivi à long terme de variables physiologiques en général. Néanmoins, les solutions présentées visent en particulier le poisson dans le cadre du projet POPSTAR qui vise à améliorer notre compréhension du comportement des poissons en analysant non seulement l’environnement dans lequel les poissons se déplacent et vivent mais aussi les poissons eux-mêmes. Après avoir identifié les défis de conception d'un système de mesure intégré par spectroscopie de bioimpédance, nous avons proposé une nouvelle architecture hybride permettant une spectroscopie rapide tout en maximisant la précision des mesures. Les blocs de génération du signal d'excitation sont critiques car leurs performances affectent l'ensemble des performances de l'architecture. La deuxième partie de cette recherche porte donc sur la conception et l’optimisation de la partie génération de l’architecture. En effet, nous avons amélioré la qualité des signaux de génération de stimuli pour les excitations mono-fréquentielle et multi-fréquentielle tout en proposant pour cela des implémentations sur puce de basse complexité. Dans la dernière partie de notre travail, la source de courant analogique qui transforme les stimuli en un courant d'excitation est discuté. Pour ce bloc, nous avons proposé une nouvelle topologie analogique utilisant un version améliorée du cascode régulé et une compensation de rétroaction du mode commun indépendante des variations du processus. Le premier prototype de puce intégrée embarquant les blocs critiques de l'architecture de mesure de bioimpédance a été conçu et simulé avec un process CMOS 0.18 µm de AMS fonctionnant sous une tension d'alimentation de 1.8 V. / Tissue composition assessment techniques are used to help better comprehend physiological processes and their overall impact on the biological state of the experiments subjects. The research presented in this manuscript aims to design a bioimpedance spectroscopy integrated measurement system capable of measuring a wide range of biomarkers over long periods of time (up to one year). The presented measurement system can be used for physiological variables long time monitoring applications in general. Nevertheless, the presented solutions target in particular fish species in the context of the POPSTAR project which aims to enhance our understanding of fish behavior by analyzing not only the environment in which fish travel and live but also the fish themselves. After identifying the design challenges of a bioimpedance spectroscopy integrated measurement system, we have proposed a novel hybrid architecture providing fast bioimpedance spectroscopy while maximizing the measurement precision. As the signal generation blocks are critical and their performances affect the whole architecture performances. The second part of this research focuses on the design and optimization of the signal generation part of the architecture. Indeed, we have enhanced the stimuli generation signals quality for single tone and multitone excitations while proposing for this blocks low complexity on-chip implementations. In the last part of our work the current driver that transforms the voltage stimuli into an excitation current is discussed. A novel analog topology using an improved regulated cascode and a common-mode feedback compensation independent of process variations is presented. The first chip prototype implementing the critical blocks of the bioimpedance integrated measurement architecture has been designed and simulated in a 0.18 µm AMS (Austria MicroSystems) CMOS process operating at 1.8 V power supply.

Integrated circuit development is an industry-driven high-risk high-stakes environment. The time from the concept of a new transistor technology to the market-ready product is measured in decades rather than months or years. This increases the risk for any company endeavouring on the journey of driving a new concept. Additionally to the return on investment being in the far future, it is only to be expected at all in high volume production, increasing the upfront investment. What makes the undertaking worthwhile are the exceptional gains that are to be expected, when the production reaches the market and enables better products. For these reasons, the adoption of new transistor technologies is usually based on small increments with foreseeable impact on the production process. Emerging semiconductor device development must be able to prove its value to its customers, the chip-producing industry, the earlier the better. With this thesis, I provide a new approach for early evaluation of emerging reconfigurable transistors in reconfigurable digital circuits. Reconfigurable transistors are a type of MOSFET that features a controllable conduction polarity, i.e., they can be configured by other input signals to work as PMOS or NMOS devices. Early device and circuit characterisation poses some challenges that are currently largely neglected by the development community. Firstly, to drive transistor development into the right direction, early feedback is necessary, which requires a method that can provide quantitative and qualitative results over a variety of circuit designs and must run mostly automatic. It should also require as little expert knowledge as possible to enable early experimentation on the device and new circuit designs together. Secondly, to actually run early, its device model should need as little data as possible to provide meaningful results. The proposed approach of this thesis tackles both challenges and employs model checking, a formal method, to provide a framework for the automated quantitative and qualitative analysis. It pairs a simple transistor device model with a charge transport model of the electrical network. In this thesis, I establish the notion of transistor-level reconfiguration and show the kinds of reconfigurable standard cell designs the device facilitates. Early investigation resulted in the discovery of certain modes of reconfiguration that the transistor features and their application to design reconfigurable standard cells. Experiments with device parameters and the design of improved combinational circuits that integrate new reconfigurable standard cells further highlight the need for a thorough investigation and quantification of the new devices and newly available standard cells. As their performance improvements are inconclusive when compared to established CMOS technology, a design space exploration of the possible reconfigurable standard cell variants and a context-aware quantitative analysis turns out to be required. I show that a charge transport model of the analogue transistor circuit provides the necessary abstraction, precision and compatibility with an automated analysis. Formalised in a DSL, it enables designers to freely characterise and combine parametrised transistor models, circuit descriptions that are device independent, and re-usable experiment setups that enable the analysis of large families of circuit variants. The language is paired with a design space exploration algorithm that explores all implementation variants of a Boolean function that employs various degrees and modes of reconfiguration. The precision of the device models and circuit performance calculations is validated against state-of-the-art FEM and SPICE simulations of production transistors. Lastly, I show that the exploration and analysis can be done efficiently using two important Boolean functions. The analysis ranges from worst-case measures, like delay, power dissipation and energy consumption to the detection and quantification of output hazards and the verification of the functionality of a circuit implementation. It ends in presenting average performance results that depend on the statistical characterisation of application scenarios. This makes the approach particularly interesting for measures like energy consumption, where average results are more interesting, and for asynchronous circuit designs which highly depend on average delay performance. I perform the quantitative analysis under various input and output load conditions in over 900 fully automated experiments. It shows that the complexity of the results warrants an extension to electronic design automation flows to fully exploit the capabilities of reconfigurable standard cells. The high degree of automation enables a researcher to use as little as a Boolean function of interest, a transistor model and a set of experiment conditions and queries to perform a wide range quantitative analyses and acquire early results.:1 Introduction 1.1 Emerging Reconfigurable Transistor Technology 1.2 Testing and Standard Cell Characterisation 1.3 Research Questions 1.4 Design Space Exploration and Quantitative Analysis 1.5 Contribution 2 Fundamental Reconfigurable Circuits 2.1 Reconfiguration Redefined 2.1.1 Common Understanding of Reconfiguration 2.1.2 Reconfiguration is Computation 2.2 Reconfigurable Transistor 2.2.1 Device geometry 2.2.2 Electrical properties 2.3 Fundamental Circuits 3 Combinational Circuits and Higher-Order Functions 3.1 Programmable Logic Cells 3.1.1 Critical Path Delay Estimation using Logical Effort Method 3.1.2 Multi-Functional Circuits 3.2 Improved Conditional Carry Adder 4 Constructive DSE for Standard Cells Using MC 4.1 Principle Operation of Model Checking 4.1.1 Model Types 4.1.2 Query Types 4.2 Overview and Workflow 4.2.1 Experiment setup 4.2.2 Quantitative Analysis and Results 4.3 Transistor Circuit Model 4.3.1 Direct Logic Network Model 4.3.2 Charge Transport Network Model 4.3.3 Transistor Model 4.3.4 Queries for Quantitative Analysis 4.4 Circuit Variant Generation 4.4.1 Function Expansion 5 Quantitative Analysis of Standard Cells 5.1 Analysis of 3-Input Minority Logic Gate 5.1.1 Circuit Variants 5.1.2 Worst-Case Analysis 5.2 Analysis of 3-Input Exclusive OR Gate 5.2.1 Worst-Case Analysis 5.2.2 Functional Verification 5.2.3 Probabilistic Analysis 6 Conclusion and Future Work 6.1 Future Work A Notational conventions B prism-gen Programming Interfaces Bibliography Terms & Abbreviations

The process of FPGA reconfiguration is to recompile a design and then update the FPGA configuration correspondingly. Traditionally, FPGA design compilation follows the way how hardware is compiled for achieving high performance, which requires a long computation time. How to efficiently compile a design becomes the bottleneck for FPGA reconfiguration. It is promising to apply some techniques or concepts from software to facilitate FPGA reconfiguration. This dissertation explores such an idea by utilizing three types of low-level manipulation on FPGA logic and routing resources, i.e. relocating, mapping/placing, and routing. It implements an FMA technique for "fast reconfiguration". The FMA makes use of the software compilation technique of reusing pre-compiled libraries for explicitly reducing FPGA compilation time. Based the software concept of Autonomic Computing, this dissertation proposes to build an Autonomous Adaptive System (AAS) to achieve "self-reconfiguration". An AAS absorbs the computing complexity into itself and compiles the desired change on its own. For routing, an FPGA router is developed. This router is able to route the MCNC benchmark circuits on five Xilinx devices within 0.35 ~ 49.05 seconds. Creating a routing-free sandbox with this router is 1.6 times faster than with OpenPR. The FMA uses relocating to load pre-compiled modules and uses routing to stitch the modules. It is an essential component of TFlow, which achieves 8 ~ 39 times speedup as compared to the traditional ISE flow on various test cases. The core part of an AAS is a lightweight embedded version of utilities for managing the system's hardware functionality. Two major utilities are mapping/placing and routing. This dissertation builds a proof-of-concept AAS with a universal UART transmitter. The system autonomously instantiates the circuit for generating the desired BAUD rate to adapt to the requirement of a remote UART receiver. / Ph. D.

The declining cost of photovoltaic (PV) modules has enabled the vision of ubiquitous photovoltaic (PV) power to become feasible. Emerging PV technologies are facilitating the creation of intentionally non-flat PV modules, which create new applications for this sustainable energy generation currently not possible with the traditional rigid, flat silicon-glass modules. However, since the photovoltaic cells are no longer coplanar, there are significant new requirements for the power electronics necessary to convert the native form of electricity into a usable form and ensure maximum energy harvest. Non-uniform insolation from cell-to-cell gives rise to non-uniform current density in the PV material, which limits the ability to create series-connected cells without bypass diode or other ways to shunt current, which is well known in the maximum power tracking literature. This thesis presents a modeling approach to determine and quantify the variations in generation of energy due to intentionally non-flat PV geometries. This will enable the power electronics circuitry to be optimized to harvest maximum energy from PV pixel elements – clusters of PV cells with similar operating characteristics. This thesis systematically compares different geometries with identical two-dimensional projection "footprints" for energy harvest throughout the day. The results show that for the same footprint, a semi-cylindrical surface harvests more energy over a typical day than a flat plate. The modeling approach is then extended to demonstrate that by using non flat geometries for PV panel, the availability of a remotely located stand-alone power system can be increased when compared to a flat panel of same footprint. These results have broad application to a variety of energy scavenging scenarios in which either total energy harvested needs to be maximized or unusual geometries for the PV active surfaces are required, including building-integrated PV. This thesis develops the analysis of the potential energy harvest gain for advanced non-planar PV collectors as a necessary first step towards the design of the power electronics circuits and control algorithms to take advantage of the new opportunities of conformal and non-flat PV collectors.

The main contribution of this thesis consists on the proposition and development a Model-driven Engineering (MDE) framework, in tandem with a component-based approach, for facilitating the design and implementation of Dynamic Partially Reconfigurable (DPR) Systems-on-Chip. The proposed methodology has been constructed around the Metadata-based Composition Framework paradigm, and based on common standards such as UML MARTE and the IEEE IP-XACT standard, an XML representation used for storing metadata about the IPs to be reused and of the platforms to be obtained at high-levels of abstraction. In fact, a componentizing process enables us to reuse the IP blocks, in UML MARTE, by wrapping them with PLB (static IPs) and proprietary (DPR blocks) interfaces. This is attained by reflecting the associated IP metadata to IP-XACT descriptions, and then to UML MARTE templates (IP reuse). Subsequently, these IP templates are used for composing a DPR model that can be exploited to create a Xilinx Platform Studio FPGA-design, through model transformations. The IP reflection and system generation chains were developed using Sodius MDWorkbench, an MDE tool conceived for the creation and manipulation of models and their meta-models, as well as the definition and execution of the associated transformation rules.

Inom miljöer med krav på hög säkerhet såsom kärnkraftverk behövs ett billigt och pålitligt alternativ för att snabbt och enkelt kunna detektera obehöriga individer vid intrång. Föreliggande rapport beskriver arbetet kring utveckling av en rörelsedetektor som har funktionen att detektera obehöriga personer inom områden där de inte har tillträde. Det slutliga målet med detta arbete är att konstruera en programmerbar krets som arbetar med signalerna från rörelsesensorn HB100, som utan underhåll kan täcka stora ytor. Arbetet har avgränsas till elektronikdesign, filterkonstruktion, EMC samt programmering av den färdiga kretsen. / Within environments with high demands on security like nuclear power plants there is a high demand on a cheap and reliable system for detection of unauthorized individuals of intrusion. This report describes the work on the development of a motion detection system using the doppler effect. The ultimate goal of this work is to design a programmable circuit that works with signals from the motion sensor HB100, which without maintenance can cover large areas. The work has been limited to electronic design, filter design, EMC and programming of the complete circuit.

Electric vehicles are increasing on the market and new technologies are being investigated because of the demand placed on electrified drivelines to provide maximum efficiency. Electric motors are expected to provide high efficiency and thus precise and compact designs of sensors for electric motors are requested. Market sensors offers a broad variety of sensors which are useful and optimal for different applications. Inductive sensors are investigated by industries because of their characteristics of having high accuracy, robustness, compact and flexible design and tolerant to harsh environments. This thesis is an investigation of inductive position sensors for automotive rotor applications,requested by one of Sweden’s largest companies within the automotive industry. The goal of the project is to design and implement theory of tradtional resolver technology on a printed circuit board (PCB) and conduct concept verifications of the system. Furthermore a new concept in the design is introduced and applied to the angular position sensor, working as a vernier scale and improve the resolution. Results and outcomes of this thesis are meant to facilitate future work and breakthroughs regarding inductive position sensors. This thesis aim to conduct a deep dive in electronics and signal processing and to derive the fundamentals of electromagnetism, from Maxwell’s equations to modern sensor design and to bring a new discussion to the table regarding the traditional measuring target used for rotor position in automotive industries. A new design working as rotor target design is presented and verified in this thesis and the results and outcomes are meant to facilitate future work and breakthroughs regarding inductive position sensors and potentially increase the accuracy and thus the efficiency of electric vehicles.

A number of non-invasive fault detection and diagnosis (FDD) techniques have been researched and have proven to have worked well in classifying faults in internal combustion engines (ICE) and other mechanical and electrical systems. These techniques are an integral step to creating more robust and accurate methods of determining where or how a fault has or will occur in such systems. These FDD techniques have the potential to not only save time avoiding a tear-down of a costly machine, but could potentially add another layer of safety in detecting and diagnosing a fault much earlier than was possible before. Looking at the previous research methods and the systems they used to acquire this data, it is a natural progression to try and make a system which is able to encapsulate all of these ideologies into one inexpensive module capable of integrating itself into the advanced set of FDD. This thesis follows along with the development of a new wireless sensor that is developed specifically for the use in FDD for ICE and other mechanical systems. A new set of software and firmware is created for the system to be able to be incorporated into previously designed algorithms. After creating and manufacturing the sensor it is put to the test by incorporating it into several Artificial Neural Networks (ANN) and comparing the results to previous experiments done with previous research equipment. Using vibration data acquired from a running engine to train a neural network, the wireless sensor was able to perform equally as well as its expensive counter parts. It proved to have the ability to achieve 100% accuracy in classifying specific engine faults. The performance of three ANN training algorithms, Levenberg-Marquardt (LM), extended Kalman Filter (EKF), and Smooth Variable Structure filter (SVSF), were tested and compared. Adding to the feasibility of a standalone system the wireless sensor was tested in a live environment as a method of instant ICE fault detection. / Thesis / Master of Applied Science (MASc)

La estimación y verificación de las prestaciones de los diseños de sistemas embebidos de la forma más rápida posible al principio del proceso de diseño es un hito de gran importancia. Por ello, esta tesis propone una nueva solución basada en simulación por anotación de código fuente, que a costa de algo de precisión, permite realizar simulaciones muy rápidas con un mínimo esfuerzo de diseño. La primera tarea realizada en esta tesis ha sido extender el lenguaje SystemC para incluir primitivas de un sistema operativo de tiempo real(RTOS) que permiten la ejecución y el refinado de módulos software. La segunda parte de la tesis se ha centrado en la generación de una librería capaz de obtener datos dinámicamente sobre las prestaciones temporales de dichos sistemas a partir del código fuente, para poder verificar el cumplimiento de las características requeridas. Junto con los elementos SW se han desarrollado componentes SystemC de alto nivel capaces de modelar los elementos principales de un sistema embebido, como buses, memorias, redes de comunicaciones, etc. Por último se han desarrollado los componentes necesarios para poder incluir toda esta infraestructura en procesos de exploración automática del proceso de diseño, de forma que en base a descripciones iniciales del sistema en formato XML. La infraestructura de simulación y estimación de rendimiento ha sido desarrollada y probada en diversos proyectos europeos. / Estimating and verifying system performance of embedded designs at the beginning of the design process is a very important task. Fast estimation tools are required in order to evaluate different design possibilities, such as HW/SW partitioning or resource allocation, to verify the fulfillment of the system constraints, or to support design space exploration flows. In this context, the thesis proposes a tool capable of simulating embedded systems using source code annotation. As a consequence, fast estimations are obtained with minimal design effort, obtaining an adequate accuracy. For developing such tool several tasks has been performed. First, the SystemC language has been extended to provide the designer with a model of a real-time operating system. This model enables the correct simulation, scheduling and debugging of embedded SW. The second element added is an infrastructure capable of estimating and annotating performance information for each basic block in the source code. This infrastructure enables obtaining timed simulations of the SW. Additionally generic TLM elements have been developed to enable creating models of the HW platforms. Finally, additional components has been developed to use the proposed tool in a complete Design Space Exploration flow. The simulation infrastructure has been developed and checked in several European projects, and in collaboration with private companies.

Sie entwickeln Entwurfssysteme für elektronische Baugruppen? Dann gehören für Sie die mit der Pinzuordnung verbundenen Optimierungskriterien - die Verdrahtbarkeit im Elektronikentwurf - zum Berufsalltag. Um die Verdrahtbarkeit unter verschiedenen Gesichtspunkten zu verbessern, werden in diesem Buch neu entwickelte Algorithmen vorgestellt. Sie ermöglichen erstmals die automatisierte Pinzuordnung für eine große Anzahl von Bauelementen in hochkomplexen Schaltungen. Alle Aspekte müssen in kürzester Zeit exakt erfasst, eingeschätzt und im Entwurfsprozess zu einem optimalen Ergebnis geführt werden. Die beschriebenen Methoden reduzieren den Entwicklungsaufwand für elektronische Systeme auf ein Minimum und ermöglichen intelligente Lösungen auf der Höhe der Zeit. Die vorliegende Arbeit behandelt die Optimierung der Pinzuordnung und die dafür notwendige Verdrahtbarkeitsvorhersage im hierarchischen Layoutentwurf. Dabei werden bekannte Methoden der Verdrahtbarkeitsvorhersage aus allen Schritten des Layoutentwurfs zusammengetragen, gegenübergestellt und auf ihre Eignung für die Pinzuordnung untersucht. Dies führt schließlich zur Entwicklung einer Vorhersagemethode, die speziell an die Anforderungen der Pinzuordnung angepasst ist. Die Pinzuordnung komplexer elektronischer Geräte ist bisher ein vorwiegend manueller Prozess. Es existieren also bereits Erfahrungen, welche jedoch weder formalisiert noch allgemein verfügbar sind. In den vorliegenden Untersuchungen werden Methoden der Pinzuordnung algorithmisch formuliert und damit einer Automatisierung zugeführt. Besondere Merkmale der Algorithmen sind ihre Einsetzbarkeit bereits während der Planung des Layouts, ihre Eignung für den hierarchisch gegliederten Layoutentwurf sowie ihre Fähigkeit, die Randbedingungen differenzieller Paare zu berücksichtigen. Die beiden untersuchten Aspekte der Pinzuordnung, Verdrahtbarkeitsvorhersage und Zuordnungsalgorithmen, werden schließlich zusammengeführt, indem die neue entwickelte Verdrahtbarkeitsbewertung zum Vergleichen und Auswählen der formulierten Zuordnungsalgorithmen zum Einsatz kommt. / This work deals with the optimization of pin assignments for which an accurate routability prediction is a prerequisite. Therefore, this contribution introduces methods for routability prediction. The optimization of pin assignments, for which these methods are needed, is done after initial placement and before routing. Known methods of routability prediction are compiled, compared, and analyzed for their usability as part of the pin assignment step. These investigations lead to the development of a routability prediction method, which is adapted to the specific requirements of pin assignment. So far pin assignment of complex electronic devices has been a predominantly manual process. Hence, practical experience exists, yet, it had not been transferred to an algorithmic formulation. This contribution develops pin assignment methods in order to automate and improve pin assignment. Distinctive characteristics of the thereby developed algorithms are their usability during layout planning, their capability to integrate into a hierarchical design flow, and the consideration of differential pairs. Both aspects, routability prediction and assignment algorithms, are finally brought together by using the newly developed routability prediction to evaluate and select the assignment algorithms.