<p>Tillståndsmaskiner är vanliga komponenter i många digitala konstruktioner. En vanlig typ av tillståndsmaskin är räknare. Räknare är ofta ganska kostsamma att implementera, med avseende på antalet grindar. För att reducera denna kostnad kan istället en PRBS (Pseudo Random Binary Sequence) användas. Denna byggs upp av ett register där en xor - operation utförs mellan två positioner, som beror på längden av registret. Resultatet från denna operation skiftas sedan in i registret. På detta sätt fås en till synes slumpmässig sekvens. Talen är dock inte på något sätt slumpmässiga utan kan hela tiden förutsägas. I detta examensarbete har en undersökning för att konstruera en billig tillståndsmaskin med hjälp av PRBS:er gjorts i MatLab. Tre olika program har skrivits för att beräkna olika kostnader vid implementering av en tillståndsmaskin.</p> / <p>Finite state machines are common components in digital designs. A common type of finite state machine is a counter. Counters are often quite expensive to implement, with respect to the number of gates. To reduce this cost, a PRBS (Pseudo Random Binary Sequence) can be used. It is constructed of a register where a xor - operation is performed between two positions, which depend on the length of the register. The result from this operation is then shifted back into the register yielding a random-like sequence. The numbers are not random, but can always be predicted. In this thesis work finite state machine using PRBS are designed in MatLab. Three different programs have been written to calculate the costs for implementation of a PRBS.</p>

<p>I 0.18 µm CMOS process har ett standardcells bibliotek med låg effektförbrukning implementerats. Cellerna har konstruerats och simulerats i Cadence och ett layoutprogram. Vid simulering av heladderare och D-vippor har effektförbrukningen och tider mätts upp och jämförts med varandra. Matningsspänningen varierade mellan 1 V och 1.8 V. In 0.18 µm CMOS process has a standard cell library with low power consumption been implemented. The cells have been made and simulated in Cadence and a layout program. At the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V.</p> / <p>A standard cell library with low power consumption has been implemented in a 0.18 mm CMOS process. The cells have been designed and simulated in Cadence and a layout program. During the simulation of the full adders and the D flip flops the power consumption and time have been estimated and compared. The power supply voltage varied between 1 V and 1.8 V.</p>

<p>DARC är ett sätt att sända digital information via FM-rundradionätet. Moduleringsmetoden för DARC är GMSK. Målsättningen var att jämföra kostnad/komplexitet och strömförbrukning för olika sätt att demodulera GMSK. Tre icke-koherenta demodulatorer och en koherent demodulator har jämförts. Man vill veta hur stor resursanvändningen var för olika FPGAer. De olika demodulatorerna har beskrivits med VHDL.</p>

<p>All large-scale digital Integrated Circuits need an appropriate strategy for clocking and synchronization. In large-scale and high-speed System-on-Chips (SoC), the traditional"Globally Synchronous"(GS) approach is not longer viable, due to severe wire delays. Instead new solutions as"Globally Synchronous, Locally Asynchronous"(GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this work, such an approach together with a circuit solution in 0.18mm CMOS process has been presented. This solution allows clocking frequencies up to 4 GHz.</p>

<p>Wireless communication is being developed in the last years day by day, there are several standards that talks about it. We are going to go through the IEEE standard 802.11 which talks about wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications. Looking this more carefully we will study MAC specifications and its environment. </p><p>The work that ISY department at Institute of Technology of Linkoping University has proposed is to design a MAC sublayer implementation for WLANs using C language programming and testing it with the test environment called “test bench”. This test bench will simulate LLC sublayer and PHY layer, in this way, our MAC implementation will has to interact with it. Therefore we will simulate a wireless network where we are going to have a short number of stations and we are going to look at carefully the MAC sublayer response in an ad hoc network.</p>

<p>The purpose of this thesis is to retarget a C compiler for a DSP processor. </p><p>Developing a new compiler from scratch is a major task. Instead, modifying an existing compiler so that it generates code for another target is a common way to develop compilers for new processors. </p><p>This is called retargeting. This thesis describes how this was done with the LCC C compiler for the Motorola DSP56002 processor.</p>

<p>This thesis investigates the possibility of realizing bandgap reference crcuits for processes having sub-1V supply voltage. With the scaling of gate oxide thickness supply voltage is getting reduced. But the threshold voltage of transistors is not getting scaled at the same rate as that of the supply voltage. This makes it difficult to incorporate conventional designs of bandgap reference circuits to processeshaving near to 1V supply voltage. In the first part of the thesis a comprehensive study on existing low voltage bandgap reference circuits is done. Using these ideas a low-power, low-voltage bandgap reference circuit is designed in the second part of the thesis work. </p><p>The proposed bandgap reference circuit is capable of generating a reference voltage of 0.730V. The circuit is implemented in 0.18µm standard CMOS technology and operates with 0.9V supply voltage, consuming 5µA current. The circuit achieves 7 ppm/K of temperature coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60C.</p>

<p>Heat, clock scew and frequency optimization are some of the problems a semiconductor designer must face. By splitting a synchrounous block into multiple pieces which comunicates asynchronously with eachother and provide them with independent clocks, these problems may be reduced. </p><p>GALS (Global Asynchronous Local Synchronous) is a wrapper that wraps a synchronous block and provides it with a clock. Multiple GALS-elements will make the whole system. The clockfrequency may be independently adjusted between each block. The clocks may be started and halted independantly depending on the workload. </p><p>Describing the system in a hardware language as VHDL, and implement it into an FPGA (Field Programmable Grid Array), makes the development of applications fast and cheap.</p>

<p>The thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity. </p><p>High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.</p>

<p>This thesis is performed at Saab Bofors Dynamics in Karlskoga and investigates a technique for ranging with laser pulses. The investigated technique is called Constant Fraction Detection (CFD). Described briefly, the received laser pulse is split into two equal parts, where one part is delayed half the pulse width and inverted. This signal is added to the original pulse. The resulting curve has the shape of a laying S and the detection of the zero level is used to stop the time measurement. The time measurement will be independent of the incoming signal’s amplitude. The CFD technique has the advantage of collecting accurate data for each send pulse, which results in an ability to collect values of measurement with a high frequency. The theses investigates a measurement frequency of 10 kHz that will give an opportunity to implement a scanning function with the possibility to, for example, reproduce a ground structure from a flying object. </p><p>The theses include both digital and analog electronics, which makes it a complex design task. The detector was constructed using analog circuits, from the signal processing of the incoming reflected pulse to the generation of a voltage level as a representation of the distance. The analog part is controlled by digital signals generated by a FPGA, which also performs calculations to convert the voltage level into a distance displayed on a LCD. </p><p>A large part of the work was dedicated to designing a layout and constructing a surface mounted printed circuit board (PCB) and therefor the report treats the whole development process, from technical requirement to construction and verification of a prototype. </p><p>The conclusion states that the CFD technique is a suitable technique for ranging with demands on fast collection of data. The prototype has sufficient accuracy at constant amplitude and was at the time of presentation shown as a prototype for demonstration. The independence of amplitude on the incoming signal was never accomplished and the reason for this is stated in the report. However, further development should solve the problem.</p>