Software-based fault tolerance techniques are a low-cost way to protect processors against soft errors. However, they introduce significant overheads to the execution time and code size, which consequently increases the energy consumption. System operating with time or energy restrictions may not be able to use these techniques. For this reason, this work proposes new software-based fault tolerance techniques with lower overheads and similar fault coverage to state-of-the-art software techniques. Thus, they can meet the system constraints. In addition, the shorter execution time reduces the exposure time to radiation. Consequently, the reliability is higher for the same fault coverage. Techniques can work with error correction or error detection. Once detection is less costly than correction, this work focuses on software-based detection techniques. Firstly, a set of data-flow techniques called VAR is proposed. The techniques are based on general building rules to allow an exhaustive assessment, in terms of reliability and overheads, of different technique variations. The rules define how the technique duplicates the code and insert checkers. Each technique uses a different set of rules. Then, a control-flow technique called SETA (Software-only Error-detection Technique using Assertions) is introduced. Comparing SETA with a state-of-the-art technique, SETA is 11.0% faster and occupies 10.3% fewer memory positions. The most promising data-flow techniques are combined with the control-flow technique in order to protect both dataflow and control-flow of the target application. To go even further with the reduction of the overheads, methods to selective apply the proposed software techniques have been developed. For the data-flow techniques, instead of protecting all registers, only a set of selected registers is protected. The set is selected based on a metric that analyzes the code and rank the registers by their criticality. For the control-flow technique, two approaches are taken: (1) removing checkers from basic blocks: all the basic blocks are protected by SETA, but only selected basic blocks have checkers inserted, and (2) selectively protecting basic blocks: only a set of basic blocks is protected. The techniques and their selective versions are evaluated in terms of execution time, code size, fault coverage, and Mean Work To Failure (MWTF), which is a metric to measure the trade-off between fault coverage and execution time. Results show that was possible to reduce the overheads without affecting the fault coverage, and for a small reduction in the fault coverage it was possible to significantly reduce the overheads. Lastly, since the evaluation of all the possible combinations for selective hardening of every application takes too much time, this work uses a method to extrapolate the results obtained by simulation in order to find the parameters for the selective combination of data and control-flow techniques that are probably the best candidates to improve the trade-off between reliability and overheads.

Les attaques par canaux auxiliaires telles que l'analyse différentielle de la consommation de courant (DPA) et l'analyse différentielle des émissions électromagnétiques (DEMA) constituent une menace sérieuse pour la sécurité des systèmes embarqués. L'objet de cette thèse est d'étudier les vulnérabilités des implantations logicielles des algorithmes cryptographiques face à ces attaques pour concevoir un processeur d'un nouveau type. Pour cela, nous commençons par identifier les différents éléments des processeurs embarqués qui peuvent être exploités pour obtenir des informations secrètes. Puis, nous introduisons des stratégies qui privilégient un équilibre entre performance et sécurité pour protéger de telles architectures au niveau transfert de registres (RTL). Nous présentons également la conception et l'implantation d'un processeur sécurisé, le SecretBlaze-SCR. Enfin, nous évaluons l'efficacité des solutions proposées contre les analyses électromagnétiques globales et locales à partir de résultats expérimentaux issus d'un prototype du SecretBlaze-SCR réalisé sur FPGA. A travers cette étude de cas, nous montrons qu'une combinaison appropriée de contre-mesures permet d'accroître significativement la résistance aux analyses par canaux auxiliaires des processeurs tout en préservant des performances satisfaisantes pour les systèmes embarqués. / Side-channel attacks such as differential power analysis (DPA) and differential electromagnetic analysis (DEMA) pose a serious threat to the security of embedded systems. The aim of this thesis is to study the side-channel vulnerabilities of software cryptographic implementations in order to create a new class of processor. For that purpose, we start by identifying the different elements of embedded processors that can be exploited to reveal the secret information. Then, we introduce several strategies that seek a balance between performance and security to protect such architectures at the register transfer level (RTL). We also present the design and implementation details of a secure processor, the SecretBlaze-SCR. Finally, we evaluate the effectiveness of the proposed solutions against global and local electromagnetic analyses from experimental results obtained with a FPGA-based SecretBlaze-SCR. Through this case study, we show that a suitable combination of countermeasures significantly increases the side-channel resistance of processors while maintaining satisfactory performance for embedded systems.

Sistemas embarcados baseados em processadores têm sido largamente aplicados em áreas críticas no que diz respeito à segurança de seres humanos e do meio ambiente. Em tais aplicações, que compreendem desde o controle de freio de carros a missões espaciais, pode ser necessária a execução confiável de todas as funcionalidades do sistema durante longos períodos e em ambientes desconhecidos, hostis ou instáveis. Mesmo em aplicações não críticas, nas quais a confiabilidade do sistema não é um requisito primordial, o usuário final deseja que seu produto apresente comportamento estável e livre de erros. Daí vem a importância de se considerar o auto-teste on-line no projeto dos sistemas embarcados atuais. Entretanto, a crescente complexidade de tais sistemas somada às fortes restrições a que eles estão sujeitos torna o projeto do auto-teste um problema cada vez mais desafiador. Em aplicações de tempo-real a dificuldade é ainda maior, uma vez que, além dos cuidados com as restrições do sistema alvo, deve-se levar em conta o atendimento dos requisitos temporais da aplicação. Entre as técnicas de auto-teste on-line atualmente pesquisadas, uma tem se destacado pela eficácia obtida a um baixo custo de projeto e sem grande impacto no atendimento dos requisitos e restrições do sistema: o auto-teste baseado em software (SBST – Software-Based Self-Test). Neste trabalho, é proposta uma metodologia para o projeto e aplicação de auto-teste on-line para processadores embarcados, considerando-se também aplicações de temporeal. Tal metodologia, denominada STEP (Self-Test for Embedded Processors), tem como base a técnica SBST e prevê o planejamento, a geração e a seleção de rotinas de teste para o processador alvo. O método proposto garante a execução periódica do autoteste, com o menor período permitido pela aplicação de tempo-real, e assegura o atendimento de todas as restrições do sistema embarcado. Além disso, a solução fornecida pelo método alcança uma boa qualidade de teste enquanto auxilia a redução de custos do sistema final. Como estudo de caso, a metodologia proposta é aplicada a diferentes arquiteturas de processadores Java e os resultados obtidos comprovam a eficiência da mesma. Por fim, é apresentada uma ferramenta que implementa a metodologia STEP, automatizando, assim, o projeto e a aplicação de auto-teste on-line para os processadores estudados. / Processor-based embedded systems have been widely used in safety-critical applications. In such applications, which include from cars break control to spatial missions, the whole system operation must be reliable during long periods even within unknown, hostile and unstable environments. In non-critical applications, system reliability is not a prime requirement, but the final user requires an error free product, with stable behavior. Hence, one can realize the importance of on-line self-testing in current embedded systems. Self-testing is becoming an important challenge due to the increasing complexity of the systems allied to their strong constraints. In real-time applications this problem becomes even more complex, since, besides meeting systems constraints, one must take into consideration the application timing requirements. Among all on-line self-testing techniques studied, Software-Based Self-Test (SBST) has been distinguished by its effectiveness, low-cost and small impact on system constraints and requirements. This work proposes a methodology for the design and implementation of on-line self-test in embedded processors, considering real-time applications. Such a methodology, called STEP (Self-Test for Embedded Processors), is based on SBST technique and encloses planning, generation and selection of test routines for the target processor. The proposed method guarantees periodical self-test execution, at the smallest period allowed by the real-time application, and ensures that all embedded system constraints are met. Furthermore, provided solution achieves high test quality while helping in the optimization of the costs of the final system. The proposed methodology is applied to different architectures of Java processors to demonstrate its efficiency. Finally, this work presents a tool that automates the design and implementation of on-line self-test in the studied processors by implementing the STEP methodology.

On-line monitoring is an important challenge in future biotechnology applications, for instance in the domain of precision livestock farming, there is need for low-cost intelligent sensors to monitor animal welfare. The common way of observing a living organism is usually done by audio-visual ways performed by a human being, who is present on the scene. This method is, however, subjective, expensive, error prone and time consuming. Instead of performing an animal observation by a human being, automated objective surveillance, by means of low cost intelligent image sensors, can be used. With the use of cheap image sensors and with the help of image analysis techniques, an automated, objective, contact-less monitoring method of the behavior of the living organisms can be provided. Much knowledge has been obtained in the development and use of image analysis algorithms to automatically quantify body features of animals, their activity rate and their behavior. Such an automatic image analysis algorithm is combined with on-line modeling techniques in order to develop an application for the recognition of several behavioral phenotypes of laying hens. The procedure is divided in two phases, where an automatic computer vision algorithm detects the monitoring object from images captured by a video camera, and then another algorithm tracks the detected object through successive frames. Further work is required to integrate these algorithms into low-cost low-energy processing platforms, including embedded systems or even wearable devices. Only then, this important biotechnology development will lead to economically applicable solutions. The challenge of the present thesis especially includes the exploration of ultra-low energy implementation platforms of this biotechnology application. The initial application is developed in the MATLAB environment and is converted to C programming language. Dynamic range and precision analysis are performed to efficiently determine the required fixed-point word-lengths of the application’s variables. Finally, platform-independent and platform-dependent code transformations and integration of the algorithm to different ASIPs (Application Specific Instruction Processors) architectures are applied in order to achieve ultimate low energy consumption. / Η On-line παρακολούθηση αποτελεί μια σημαντική πρόκληση στις μελλοντικές βιοτεχνολογικές εφαρμογές, όπως παραδείγματος χάριν στον τομέα της κτηνοτροφίας, όπου είναι επιτακτική η ανάγκη χρήσης χαμηλού κόστους έξυπνων αισθητήρων στην παρακολούθηση της ευημερίας των ζωντανών οργανισμών. Ο συνήθης τρόπος παρακο-λούθησης ενός ζωντανού οργανισμού συνίσταται στη χρήση οπτικοακουστικών μέσων, τα οποία χειρίζεται ο ανθρώπινος παράγοντας που είναι παρόν. Η μέθοδος αυτή είναι κατά κύριο λόγο υποκειμενική, ακριβή, επιρρεπής σε σφάλματα και επιπροσθέτως χρονοβόρα. Αντ’ αυτού είναι δυνατό να εφαρμοσθεί μια αυτοματοποιημένη αντι-κειμενική επιτήρηση, η οποία λαμβάνει χώρα μέσω χαμηλού κόστους έξυπνων αισθητήρων εικόνας. Η χρήση των αισθητήρων, σε συνδυασμό με τη βοήθεια τεχνικών ανάλυσης εικόνας, παράγει μια αυτόματη αντικειμενική και εξ’ αποστάσεως μέθοδο πα-ρακολούθησης της συμπεριφοράς των ζωντανών οργανισμών. Τα τελευταία χρόνια η τεχνογνωσία στην ανάπτυξη και τη χρήση αλγορίθμων επεξεργασίας εικόνας, οι οποίοι εντοπίζουν αυτόματα τα χαρακτηριστικά των σωμάτων των ζωντανών οργανισμών, το ποσοστό δραστηριότητάς τους, καθώς και την συμπε-ριφορά τους, αναπτύσσεται ραγδαία. Ένας τέτοιος αλγόριθμος συνδυάζεται με on-line τεχνικές μοντελοποίησης αποσκοπώντας στην αναγνώριση διαφόρων φαινοτύπων συ-μπεριφοράς των ορνίθων. Η διαδικασία χωρίζεται σε δύο φάσεις, όπου κατά την πρώτη ένας αλγόριθμος με υπολογιστική όραση ανιχνεύει το αντικέιμενο παρακολούθησης από εικόνες που προέρχονται από μια κάμερα παρακολούθησης, και κατά τη δεύτερη ένας αλγόριθμος εντοπισμού αναλαμβάνει την παρακολούθηση του αντικειμένου σε δια-δοχικές εικόνες. Ακολούθως, είναι επιτακτική η υλοποίηση των αλγορίθμων σε χαμηλού κόστους χαμηλής κατανάλωσης πλατφόρμες επεξεργασίας, οι οποίες μπορούν να περιλαμβάνουν ενσωματωμένα ή ακόμα και ασύρματα συστήματα, ούτως ώστε η σημαντική αυτή βιοτεχνολογική ανάπτυξη να οδηγήσει σε οικονομικά εφικτές λύσεις. Η παρούσα μελέτη ανταπεξέρχεται στην πρόκληση της εξερεύνησης χαμηλής κατανάλωσης υλοποίησεων της βιοτεχνολογικής αυτής εφαρμογής. Η εφαρμογή έχει αναπτυχθεί σε υπολογιστικό περιβάλλον Matlab και εν συνεχεία ακολουθεί η μετάφρασή της σε C προγραμματιστική γλώσσα. Επιπρόσθετα, εφαρ-μόσθηκε δυναμική ανάλυση του εύρους και ανάλυση της ακρίβειας των μεταβλητών, με στόχο τον προσδιορισμό των μηκών των fixed point λέξεων. Εν κατακλείδι, πραγμα-τοποιήθηκαν platform-independent και platform-dependent μετασχηματισμοί της εφαρμογής και υλοποιείται σε διαφορετικές ASIP αρχιτεκτονικές αποσκοπώντας στην επίτευξη χαμηλής κατανάλωσης ενέργειας.

Sistemas embarcados baseados em processadores têm sido largamente aplicados em áreas críticas no que diz respeito à segurança de seres humanos e do meio ambiente. Em tais aplicações, que compreendem desde o controle de freio de carros a missões espaciais, pode ser necessária a execução confiável de todas as funcionalidades do sistema durante longos períodos e em ambientes desconhecidos, hostis ou instáveis. Mesmo em aplicações não críticas, nas quais a confiabilidade do sistema não é um requisito primordial, o usuário final deseja que seu produto apresente comportamento estável e livre de erros. Daí vem a importância de se considerar o auto-teste on-line no projeto dos sistemas embarcados atuais. Entretanto, a crescente complexidade de tais sistemas somada às fortes restrições a que eles estão sujeitos torna o projeto do auto-teste um problema cada vez mais desafiador. Em aplicações de tempo-real a dificuldade é ainda maior, uma vez que, além dos cuidados com as restrições do sistema alvo, deve-se levar em conta o atendimento dos requisitos temporais da aplicação. Entre as técnicas de auto-teste on-line atualmente pesquisadas, uma tem se destacado pela eficácia obtida a um baixo custo de projeto e sem grande impacto no atendimento dos requisitos e restrições do sistema: o auto-teste baseado em software (SBST – Software-Based Self-Test). Neste trabalho, é proposta uma metodologia para o projeto e aplicação de auto-teste on-line para processadores embarcados, considerando-se também aplicações de temporeal. Tal metodologia, denominada STEP (Self-Test for Embedded Processors), tem como base a técnica SBST e prevê o planejamento, a geração e a seleção de rotinas de teste para o processador alvo. O método proposto garante a execução periódica do autoteste, com o menor período permitido pela aplicação de tempo-real, e assegura o atendimento de todas as restrições do sistema embarcado. Além disso, a solução fornecida pelo método alcança uma boa qualidade de teste enquanto auxilia a redução de custos do sistema final. Como estudo de caso, a metodologia proposta é aplicada a diferentes arquiteturas de processadores Java e os resultados obtidos comprovam a eficiência da mesma. Por fim, é apresentada uma ferramenta que implementa a metodologia STEP, automatizando, assim, o projeto e a aplicação de auto-teste on-line para os processadores estudados. / Processor-based embedded systems have been widely used in safety-critical applications. In such applications, which include from cars break control to spatial missions, the whole system operation must be reliable during long periods even within unknown, hostile and unstable environments. In non-critical applications, system reliability is not a prime requirement, but the final user requires an error free product, with stable behavior. Hence, one can realize the importance of on-line self-testing in current embedded systems. Self-testing is becoming an important challenge due to the increasing complexity of the systems allied to their strong constraints. In real-time applications this problem becomes even more complex, since, besides meeting systems constraints, one must take into consideration the application timing requirements. Among all on-line self-testing techniques studied, Software-Based Self-Test (SBST) has been distinguished by its effectiveness, low-cost and small impact on system constraints and requirements. This work proposes a methodology for the design and implementation of on-line self-test in embedded processors, considering real-time applications. Such a methodology, called STEP (Self-Test for Embedded Processors), is based on SBST technique and encloses planning, generation and selection of test routines for the target processor. The proposed method guarantees periodical self-test execution, at the smallest period allowed by the real-time application, and ensures that all embedded system constraints are met. Furthermore, provided solution achieves high test quality while helping in the optimization of the costs of the final system. The proposed methodology is applied to different architectures of Java processors to demonstrate its efficiency. Finally, this work presents a tool that automates the design and implementation of on-line self-test in the studied processors by implementing the STEP methodology.

Sistemas embarcados baseados em processadores têm sido largamente aplicados em áreas críticas no que diz respeito à segurança de seres humanos e do meio ambiente. Em tais aplicações, que compreendem desde o controle de freio de carros a missões espaciais, pode ser necessária a execução confiável de todas as funcionalidades do sistema durante longos períodos e em ambientes desconhecidos, hostis ou instáveis. Mesmo em aplicações não críticas, nas quais a confiabilidade do sistema não é um requisito primordial, o usuário final deseja que seu produto apresente comportamento estável e livre de erros. Daí vem a importância de se considerar o auto-teste on-line no projeto dos sistemas embarcados atuais. Entretanto, a crescente complexidade de tais sistemas somada às fortes restrições a que eles estão sujeitos torna o projeto do auto-teste um problema cada vez mais desafiador. Em aplicações de tempo-real a dificuldade é ainda maior, uma vez que, além dos cuidados com as restrições do sistema alvo, deve-se levar em conta o atendimento dos requisitos temporais da aplicação. Entre as técnicas de auto-teste on-line atualmente pesquisadas, uma tem se destacado pela eficácia obtida a um baixo custo de projeto e sem grande impacto no atendimento dos requisitos e restrições do sistema: o auto-teste baseado em software (SBST – Software-Based Self-Test). Neste trabalho, é proposta uma metodologia para o projeto e aplicação de auto-teste on-line para processadores embarcados, considerando-se também aplicações de temporeal. Tal metodologia, denominada STEP (Self-Test for Embedded Processors), tem como base a técnica SBST e prevê o planejamento, a geração e a seleção de rotinas de teste para o processador alvo. O método proposto garante a execução periódica do autoteste, com o menor período permitido pela aplicação de tempo-real, e assegura o atendimento de todas as restrições do sistema embarcado. Além disso, a solução fornecida pelo método alcança uma boa qualidade de teste enquanto auxilia a redução de custos do sistema final. Como estudo de caso, a metodologia proposta é aplicada a diferentes arquiteturas de processadores Java e os resultados obtidos comprovam a eficiência da mesma. Por fim, é apresentada uma ferramenta que implementa a metodologia STEP, automatizando, assim, o projeto e a aplicação de auto-teste on-line para os processadores estudados. / Processor-based embedded systems have been widely used in safety-critical applications. In such applications, which include from cars break control to spatial missions, the whole system operation must be reliable during long periods even within unknown, hostile and unstable environments. In non-critical applications, system reliability is not a prime requirement, but the final user requires an error free product, with stable behavior. Hence, one can realize the importance of on-line self-testing in current embedded systems. Self-testing is becoming an important challenge due to the increasing complexity of the systems allied to their strong constraints. In real-time applications this problem becomes even more complex, since, besides meeting systems constraints, one must take into consideration the application timing requirements. Among all on-line self-testing techniques studied, Software-Based Self-Test (SBST) has been distinguished by its effectiveness, low-cost and small impact on system constraints and requirements. This work proposes a methodology for the design and implementation of on-line self-test in embedded processors, considering real-time applications. Such a methodology, called STEP (Self-Test for Embedded Processors), is based on SBST technique and encloses planning, generation and selection of test routines for the target processor. The proposed method guarantees periodical self-test execution, at the smallest period allowed by the real-time application, and ensures that all embedded system constraints are met. Furthermore, provided solution achieves high test quality while helping in the optimization of the costs of the final system. The proposed methodology is applied to different architectures of Java processors to demonstrate its efficiency. Finally, this work presents a tool that automates the design and implementation of on-line self-test in the studied processors by implementing the STEP methodology.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes a system in which multiple embedded processors are used for real-time processing of telemetry streams from satellites and radars. Embedded EPC-5 modules are plugged into VME slots in a Loral System 550. Telemetry streams are acquired and decommutated by the System 550, and selected parameters are packetized and appended to a mailbox which resides in VME memory. A Windows-based program continuously fetches packets from the mailbox, processes the data, writes to log files, displays processing results on screen, and sends messages via a modem connected to a serial port.

No description available.

The main focus of this dissertation thesis is on methods and tools which can increase the speed of software development process for embedded processors used in mechatronics applications. The first part of this work introduces software and hardware tools suitable for a rapid development and prototyping of new applications used today. This work focuses on two main topics from the mentioned application field. The first topic is a development of tools for an automatic code generation from the Simulink environment for an embedded processor. The second topic is a development of tools enabling execution time prediction based on a Simulink model. Next chapter of this work describes various aspects and properties of the Cerebot blockset, which is a toolset for a fully automatic code generation from a Simulink environment for an embedded processor. Following chapter describes various methods that are suitable for predicting the execution time on an embedded processor based on a Simulink model. Main contribution of this work presents the created support for a fully automatic code generation from a Simulink software for the MX7 cK hardware, which enables a code generation supporting also a complex peripheral (a graphic display unit). The next important contribution of this work presents the developed method for an automatic prediction of the software execution time based on a Simulink model.

Cette thèse vise à définir une méthodologie de mise en œuvre d’applications performantes sur les processeurs embarqués du futur. Ces architectures nécessitent notamment d’exploiter au mieux les différents niveaux de parallélisme (grain fin, gros grain) et de gérer les communications et les accès à la mémoire. Pour étudier cette méthodologie, nous avons utilisé un processeur cible représentatif de ces architectures émergentes, le processeur CELL. Le détecteurde points d’intérêt de Harris est un exemple de traitement régulier nécessitant des unités de calcul intensif. En étudiant plusieurs schémas de mise en oeuvre sur le processeur CELL, nous avons ainsi pu mettre en évidence des méthodes d’optimisation des calculs en adaptant les programmes aux unités spécifiques de traitement SIMD du processeur CELL. L’utilisation efficace de la mémoire nécessite par ailleurs, à la fois une bonne exploitation des transferts et un arrangement optimal des données en mémoire. Nous avons développé un outil d’abstraction permettant de simplifier et d’automatiser les transferts et la synchronisation, CELL MPI. Cette expertise nous a permis de développer une méthodologie permettant de simplifier la mise en oeuvre parallèle optimisée de ces algorithmes. Nous avons ainsi conçu un outil de programmation parallèle à base de squelettes algorithmiques : SKELL BE. Ce modèle de programmation propose une solution originale de génération d’applications à base de métaprogrammation. Il permet, de manière automatisée, d’obtenir de très bonnes performances et de permettre une utilisation efficace de l’architecture, comme le montre la comparaison pour un ensemble de programmes test avec plusieurs autres outils dédiés à ce processeur. / This thesis aims to define a design methodology for high performance applications on future embedded processors. These architectures require an efficient usage of their different level of parallelism (fine-grain, coarse-grain), and a good handling of the inter-processor communications and memory accesses. In order to study this methodology, we have used a target processor which represents this type of emerging architectures, the Cell BE processor.We have also chosen a low level image processing application, the Harris points of interest detector, which is representative of a typical low level image processing application that is highly parallel. We have studied several parallelisation schemes of this application and we could establish different optimisation techniques by adapting the software to the specific SIMD units of the Cell processor. We have also developped a library named CELL MPI that allows efficient communication and synchronisation over the processing elements, using a simplified and implicit programming interface. This work allowed us to develop a methodology that simplifies the design of a parallel algorithm on the Cell processor.We have designed a parallel programming tool named SKELL BE which is based on algorithmic skeletons. This programming model providesan original solution of a meta-programming based code generator. Using SKELL BE, we can obtain very high performances applications that uses the Cell architecture efficiently when compared to other tools that exist on the market.